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FeaTures
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LTC2978 Octal PMBus Power Supply Monitor and Controller with EEPROM DescripTion
The LTC(R)2978 is an octal, PMBus compliant power supply monitor, supervisor, sequencer and margin controller. PMBus functions include warning and fault OV/UV threshold pairs for eight output channels and one input channel. Programmable fault response allows the power supplies to be disabled with optional retry after a fault has been detected. PMBus reads allow eight output voltages and one input voltage to be monitored. In addition, odd numbered channels can substitute sense resistor voltage measurements for output voltage measurements. PMBus commands support power supply sequencing and precision point-of-load voltage servo to one of three programmed values: margin high, margin low and nominal. A programmable watchdog timer monitors microprocessor activity for a stalled condition and resets the micro if necessary. The 1-wire synchronization bus supports power supply sequencing across multiple LTC2978 devices. User programmable parameters can be stored in EEPROM. Voltage supervisor, voltage monitor and temperature faults can also be logged to EEPROM.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7382203 and 7420359.
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n n n n
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PMBus Compliant Interface and Command Set Configuration EEPROM Fault Logging to Internal EEPROM Differential Input, 15-Bit ADC with Less Than 0.25% of Total Unadjusted Error Monitors Eight Output Channels and One Input Voltage 8-Channel Sequencer Programmable Watchdog Timer Eight UV/OV Voltage Supervisors Eight 10-Bit Voltage-Buffered IDACs with Soft Connect Linear, Voltage Servo Adjusts Supply Voltages by Ramping Voltage-Buffered IDAC Outputs Up/Down Supports Multichannel Fault Management On-Chip Digital Temperature Sensor Available in 64-Pin 9mm x 9mm QFN Package
applicaTions
n n
Computers Network Servers
Typical applicaTion
Octal Power Supply Controller with PMBus Interface
4.5V < VIBUS < 15V TO INTERMEDIATE BUS CONVERTER ENABLE VPWR VIN_EN VIN_SNS VDACP0 VSENSEP0 SDA PMBus INTERFACE SCL ALERTB CONTROL0 WRITE-PROTECT TO/FROM OTHER LTC2978s WP FAULTB00 SHARE_CLK GND
2978 TA01
VIN VOUT R20 7.5k LOAD VDACM0 VSENSEM0 VOUT_EN0 PWRGD WDI/RESETB ASEL0 ASEL1 *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN TO P RESETB INPUT WATCHDOG TIMER INTERRUPT R10 20k R30 41.2k DIGITALLY MANAGED POWER SUPPLY
LTC2978*
VFB
SGND RUN/SS GND
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LTC2978 Table oF conTenTs
Features .............................................................................................................................1 Applications ........................................................................................................................1 Typical Application ................................................................................................................1 Description..........................................................................................................................1 Absolute Maximum Ratings ......................................................................................................3 Order Information ..................................................................................................................3 Pin Configuration ..................................................................................................................3 Electrical Characteristics .........................................................................................................4 Timing Diagram ....................................................................................................................8 Typical Performance Characteristics ...........................................................................................8 Pin Functions ..................................................................................................................... 12 Block Diagram.................................................................................................................... 14 Operation.......................................................................................................................... 15 Operation Overview ...............................................................................................................................................15 PMBus Serial Digital Interface ...............................................................................................................................16 Register Command Set ..........................................................................................................................................18 Detailed PMBus Command Register Descriptions .................................................................................................22 Manufacturer Specific Commands .........................................................................................................................35 Watchdog ..............................................................................................................................................................49 Reset .....................................................................................................................................................................49 Write-Protect Pin ...................................................................................................................................................49 Other Operations....................................................................................................................................................49 Applications Information ....................................................................................................... 50 PCB Assembly and Layout Suggestions ................................................................................................................61 Typical Application .............................................................................................................. 62 Package Description ............................................................................................................ 63 Typical Application .............................................................................................................. 64 Related Parts ..................................................................................................................... 64
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LTC2978 absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTion
64 VSENSEP6 63 VSENSEM5 62 VSENSEP5 61 VDACM7 60 VDACP7 59 VDACP6 58 VDACM6 57 VDACM5 56 VDACP5 55 VDACP4 54 VDACM4 53 VSENSEM4 52 VSENSEP4 51 VDACM3 50 VDACP3 49 VSENSEM3 VSENSEM6 1 VSENSEP7 2 VSENSEM7 3 VOUT_EN0 4 VOUT_EN1 5 VOUT_EN2 6 VOUT_EN3 7 VOUT_EN4 8 VOUT_EN5 9 VOUT_EN6 10 VOUT_EN7 11 VIN_EN 12 DNC 13 VIN_SNS 14 VPWR 15 VDD33 16 65 48 VSENSEP3 47 VSENSEM2 46 VSENSEP2 45 VDACM2 44 VDACP2 43 VSENSEM1 42 VSENSEP1 41 VDACM1 40 VDACP1 39 VDACP0 38 VDACM0 37 VSENSEM0 36 VSENSEP0 35 REFM 34 REFP 33 ASEL1 UP PACKAGE 64-LEAD (9mm 9mm) PLASTIC QFN TJMAX = 125C, JA = 28C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB TOP VIEW
Supply Voltages: VPWR to GND ......................................... -0.3V to 15V VIN_SNS to GND ..................................... -0.3V to 15V VDD33 to GND ....................................... -0.3V to 3.6V VDD25 to GND ..................................... -0.3V to 2.75V Digital Input/Output Voltages: ALERTB, SDA, SCL, CONTROL0, CONTROL1............................................ -0.3V to 5.5V PWRGD, SHARE_CLK, WDI, WP ..................................-0.3V to VDD33 + 0.3V FAULTB00, FAULTB01, FAULTB10, FAULTB11 ................................-0.3V to VDD33 + 0.3V ASEL0, ASEL1 ..........................-0.3V to VDD33 + 0.3V Analog Voltages: REFP ................................................... -0.3V to 1.35V REFM to GND........................................ -0.3V to 0.3V VSENSEP[7:0] to GND ................................. -0.3V to 6V VSENSEM[7:0] to GND ................................ -0.3V to 6V VOUT_EN[3:0], VIN_EN to GND .................. -0.3V to 15V VOUT_EN[7:4] to GND ................................. -0.3V to 6V VDACP[7:0] to GND .................................... -0.3V to 6V VDACM[7:0] to GND ............................... -0.3V to 0.3V Operating Temperature Range: LTC2978C ................................................ 0C to 70C LTC2978I .............................................-40C to 85C Storage Temperature Range .................. -65C to 125C
orDer inForMaTion
LEAD FREE FINISH LTC2978CUP#PBF LTC2978IUP#PBF TAPE AND REEL LTC2978CUP#TRPBF LTC2978IUP#TRPBF PART MARKING* LTC2978 LTC2978 PACKAGE DESCRIPTION 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
VDD33 17 VDD25 18 WP 19 PWRGD 20 SHARE_CLK 21 WDI/RESET 22 FAULTB00 23 FAULTB01 24 FAULTB10 25 FAULTB11 26 SDA 27 SCL 28 ALERTB 29 CONTROL0 30 CONTROL1 31 ASEL0 32
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LTC2978 elecTrical characTerisTics
SYMBOL PARAMETER Power-Supply Characteristics VPWR VPWR Supply Input Operating Range IPWR VPWR Supply Current IVDD33 VDD33 Supply Current VUVLO_VDD33 VDD33 Undervoltage Lockout VDD33 Undervoltage Lockout Hysteresis VDD33 Supply Input Operating Range Regulator Output Voltage Regulator Output Short-Circuit Current VDD25 Regulator Output Voltage Regulator Output Short-Circuit Current Voltage Reference Characteristics VREF Output Voltage Temperature Coefficient Hysteresis ADC Characteristics VIN_ADC Voltage Sense Input Range
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VPWR = VIN_SNS = 12V, VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF CVDD25 = 100nF and CREF = 100nF , .
CONDITIONS
l
MIN 4.5
TYP
MAX 15 13 13 2.8
UNITS V mA mA V mV V V mA V mA V ppm/C ppm
4.5V VPWR 15V, VDD33 Floating 3.13V VDD33 3.47V, VPWR = VDD33 VDD33 Ramping Up, VPWR = VDD33
l l l
2.35
10 10 2.55 120
VPWR = VDD33 4.5V VPWR 15V VPWR = 4.5V, VDD33 = 0V 3.13V VDD33 3.47V VPWR = VDD33 = 3.47V, VDD25 = 0V
l l l l l
3.13 3.13 75 2.35 30
3.26 90 2.5 55 1.232 3 100
3.47 3.47 140 2.6 80
(Note 3) Differential Voltage: VIN_ADC = (VSENSEPn - VSENSEMn) Single-Ended Voltage: VSENSEMn Single-Ended Voltage: VSENSEPn, VSENSEMn Differential Voltage: VIN_ADC 0V VIN_ADC 6V 0mV |VIN_ADC| < 16mV 16mV |VIN_ADC| < 32mV 32mV |VIN_ADC| < 63.9mV 63.9mV |VIN_ADC| < 127.9mV 127.9mV |VIN_ADC| VIN_ADC 1.8V (Note 4 ) Voltage Sense Mode (Note 5) Current Sense Mode, Odd Numbered Channels Only, 15.6V/LSB (Note 5) Voltage Sense Mode Current Sense Mode, Odd Numbered Channels Only Voltage Sense Mode Current Sense Mode, Odd Numbered Channels Only Voltage Sense Mode, VIN_ADC = 6V Current Sense Mode, Odd Numbered Channels Only, VIN_ADC = 0.17V Voltage Sense Mode (Note 6) Current Sense Mode (Note 6) Temperature Input (Note 6)
l l l l
0 -0.1 -0.1 -170 122 15.625 31.25 62.5 125 250
6 0.1 6 170
V V V mV V/LSB V/LSB V/LSB V/LSB V/LSB V/LSB % V V V V V V % % ms ms ms pF kHz
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N_ADC
Current Sense Input Range (Odd Numbered Channels Only When So Configured) Voltage Sense Resolution Current Sense Resolution (Odd Numbered Channels Only When So Configured) Total Unadjusted Error Integral Nonlinearity
TUE_ADC INL_ADC
l l l l l l l l l
0.25 854 31.3 400 31.3 250 35 0.2 0.2 6.15 24.6 24.6 1 62.5
DNL_ADC
Differential Nonlinearity
VOS_ADC
Offset Error
GAIN_ADC
Gain Error
tCONV_ADC
Conversion Time
CIN_ADC fIN_ADC
Input Sampling Capacitance Input Sampling Frequency
LTC2978 elecTrical characTerisTics
SYMBOL IIN_ADC PARAMETER Input Leakage Current Differential Input Current Voltage Buffered IDAC Output Characteristics N_VDACP Resolution VFS_VDACP Full-Scale Output Voltage (Programmable) INL_VDACP Integral Nonlinearity DNL_VDACP Differential Nonlinearity VOS_VDACP Offset Voltage VDACP Load Regulation (VDACPn - VDACMn) PSRR (VDACPn - VDACMn) DC CMRR (VDACPn - VDACMn) Leakage Current Short-Circuit Current Low Short-Circuit Current High COUT Output Capacitance tS_VDACP DAC Output Update Rate Voltage Supervisor Characteristics VIN_VS Input Voltage Range (Programmable)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF CVDD25 = 100nF and CREF = 100nF , .
CONDITIONS VIN_ADC = 0V, 0V VCOMMONMODE 6V, Current Sense Mode VIN_ADC = 0.17V, Current Sense Mode VIN_ADC = 6V, Voltage Sense Mode MIN
l l l
TYP
MAX 0.5 250 15
UNITS A nA A Bits V V LSB LSB mV ppm/mA ppm/mA dB dB dB nA mA mA pF s V V V mV/LSB mV/LSB % % % s V k % % % % mV C
80 10 10 1.38 2.65
DAC Code = 0x3FF Buffer Gain Setting_0 DAC Polarity = 1 Buffer Gain Setting_1 (Note 7) (Note 7) (Note 7) VDACPn = 2.65V, IVDACPn Sourcing = 2mA VDACPn = 0.1V, IVDACPn Sinking = 2mA DC: 3.13V VDD33 3.47V, VPWR = VDD33 100mV Step in 20ns with 50pF Load -0.1V VDACMn 0.1V VDACPn Hi-Z, 0V VDACPn 6V VDACPn Shorted to GND VDACPn Shorted to VDD33 VDACPn Hi-Z Fast Servo Mode VIN_VS = (VSENSEPn Low Resolution Mode - VSENSEMn) High Resolution Mode Single-Ended Voltage: VSENSEMn 0V to 3.8V Range: High Resolution Mode 0V to 6V Range: Low Resolution Mode 2V VIN_VS 6V, Low Resolution Mode 1.5V < VIN_VS 3.8V, High Resolution Mode 0.8V VIN_VS 1.5V, High Resolution Mode
l l l l l
1.32 2.53
1.44 2.77 2 2.4 10
100 100 60 40 60
l l l
-10 4 10 250
100 -4 10
l l l
0 0 -0.1 4 8
6 3.8 0.1
N_VS TUE_VS
Voltage Sensing Resolution Total Unadjusted Error
l l l
1.25 1.0 1.5 12.21
tS_VS Update Rate VIN_SNS Input Characteristics VVIN_SNS VIN_SNS Input Voltage Range RVIN_SNS VIN_SNS Input Resistance TUEVIN_SNS VIN_ON, VIN_OFF Threshold Total Unadjusted Error
l l l l l l
0 70
90
3V VVIN_SNS 8V VVIN_SNS > 8V READ_VIN Total Unadjusted Error 3V VVIN_SNS 8V VVIN_SNS > 8V Voltage Buffered IDAC Soft-Connect Comparator Characteristics VOS_CMP Offset Voltage Temperature Sensor Characteristics TUE_TS Total Unadjusted Error VOUT Enable Output (VOUT_EN [3:0]) Characteristics VVOUT_ENn Output High Voltage IVOUT_ENn = -5A, VDD33 = 3.3V
15 110 2.0 1.0 1.5 1.0 18
l
3 1
l
11.6
12.5
14.7
V
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LTC2978 elecTrical characTerisTics
SYMBOL IVOUT_ENn PARAMETER Output Sourcing Current Output Sinking Current
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF CVDD25 = 100nF and CREF = 100nF , .
CONDITIONS VVOUT_ENn Pull-Up Enabled, VVOUT_ENn = 1V Strong Pull-Down Enabled, VVOUT_ENn = 0.4V Weak Pull-Down Enabled, VVOUT_ENn = 0.4V Internal Pull-Up Disabled, 0V VVOUT_ENn 15V Strong Pull-Down Enabled, VOUT_ENn = 0.1V 0V VVOUT_ENn 6V IVIN_EN = -5A, VDD33 = 3.3V VIN_EN Pull-Up Enabled, VVIN_EN = 1V Strong Pull-Down Enabled, VVIN_EN = 0.4V Weak Pull-Down Enabled, VVIN_EN = 0.4V Internal Pull-Up Disabled, 0V VVIN_EN 15V
l l l l
MIN -5 3 33
TYP -6 5 50
MAX -8 8 60 1
UNITS A mA A A
Output Leakage Current VOUT Enable Output (VOUT_EN [7:4]) Characteristics IVOUT_ENn Output Sinking Current Output Leakage Current VIN Enable Output (VIN_EN) Characteristics VVIN_EN Output High Voltage IVIN_EN Output Sourcing Current Output Sinking Current Leakage Current EEPROM Characteristics Endurance (Note 8)
l l
3
6
9 1
mA A V A mA A A
l l l l l
11.6 -5 3 33
12.5 -6 5 50
14.7 -8 8 60 1
l 0C < TJ < 85C During EEPROM Write 10,000 Operations l Retention (Note 8) TA < 85C 10 Mass_Write Mass Write Operation Time (Note 9) STORE_USER_ALL, 0C < TJ < 85C During l EEPROM Write Operations Digital Inputs SCL, SDA, CONTROL0, CONTROL1, WDI/RESETB, FAULTB00, FAULTB01, FAULTB10, FAULTB11, WP
Cycles Years ms
440
4100
VIH VIL VHYST ILEAK
High Level Input Voltage Low Level Input Voltage Input Hysteresis Input Leakage Current
l l
2.1 1.5 20 2 2 10 98
V V mV A A s ns s s MHz pF V V kHz s ns A pF
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tSP
Pulse Width of Spike Suppressed
tRESETB Pulse Width to Assert Reset tWDI Pulse Width to Reset Watchdog Timer fWDI Watchdog Interrupt Input Frequency CIN Digital Input Capacitance Digital Input SHARE_CLK VIH High Level Input Voltage VIL Low Level Input Voltage fSHARE_CLK_IN Input Frequency Operating Range tLOW Assertion Low Time tRISE Rise Time ILEAK Input Leakage Current CIN Input Capacitance
0V VPIN 5.5V, SDA, SCL, CONTROLx Pins Only 0V VPIN VDD33 + 0.3V, FAULTBxx, WDI/RESETB, WP Pins Only FAULTBxx, CONTROLx Pins Only SDA, SCL Pins Only VWDI/RESETB 1.5V VWDI/RESETB 1.5V
l l
l l l
300 0.3 10
200 1
l l l
1.6 90 0.825 0.8 110 1.1 450 1 10
VSHARE_CLK < 0.8V VSHARE_CLK < 0.8V to VSHARE_CLK > 1.6V 0V VSHARE_CLK VDD33 + 0.3V
l l l
LTC2978 elecTrical characTerisTics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF CVDD25 = 100nF and CREF = 100nF , .
SYMBOL PARAMETER CONDITIONS Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11 VOL Digital Output Low Voltage ISINK = 3mA fSHARE_CLK_OUT Output Frequency Operating Range 5.49k Pull-Up to VDD33 Digital Inputs ASEL0,ASEL1 VIH Input High Threshold Voltage VIL Input Low Threshold Voltage IIH,IL High, Low Input Current ASEL[1:0] = 0, VDD33 IIH, Z Hi-Z Input Current CIN Input Capacitance Serial Bus Timing Characteristics fSCL Serial Clock Frequency (Note 10) tLOW Serial Clock Low Period (Note 10) tHIGH Serial Clock High Period (Note 10) tBUF Bus Free Time Between Stop and Start (Note 10) tHD,STA Start Condition Hold Time (Note 10) tSU,STA Start Condition Setup Time (Note 10) tSU,STO Stop Condition Setup Time (Note 10) tHD,DAT Data Hold Time (LTC2978 Receiving Data) (Note 10) Data Hold Time (LTC2978 Transmitting Data) (Note 10) tSU,DAT Data Setup Time (Note 10) tSP Pulse Width of Spike Suppressed (Note 10) tTIMEOUT_BUS Time Allowed to Complete any PMBus Longer Timeout = 0 Command After Which Time SDA Will Longer Timeout = 1 Be Released and Command Terminated Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. If power is supplied to the chip via the VDD33 pin only, connect VPWR and VDD33 pins together. Note 3: Hysteresis in the output voltage is created by package stress that differs depending on whether the IC was previously at a higher or lower temperature. Output voltage is always measured at 25C, but the IC is cycled to 85C or -40C before successive measurements. Hysteresis is roughly proportional to the square of the temperature change. Note 4: TUE(%) is defined as: Gain Error (%) + 100 * (INL + VOS)/VIN. Note 5: Integral nonlinearity (INL) is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve (0V and 6V). The deviation is measured from the center of the quantization band. MIN
l l
TYP
MAX 0.4 110
UNITS V kHz V V A A pF kHz s s s ns ns ns ns
90 VDD33 - 0.5
100
l l l l
0.5 95 24 10
l l l l l l l l l l
10 1.3 0.6 1.3 600 600 600 0 300 100 98
400
900
ns ns ns
l l
25 200
35 280
ms ms
Note 6: The time between successive ADC conversions (latency of the ADC) for any given channel is given as: 36.9ms + (6.15ms * number of ADC channels configured in Low Resolution mode) + (24.6ms * number of ADC channels configured in High Resolution mode). Note 7: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to full-scale code, 1023. Note 8: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification. Note 9: The LTC2978 will not acknowledge any PMBus write commands when a STORE_USER_ALL command is being executed. Note 10: Maximum capacitive load, CB, for SCL and SDA is 400pF Data . and clock rise time (tr) and fall time (tf) are: (20 + 0.1* CB) (ns) < tr < 300ns and (20 + 0.1 * CB) (ns) < tf < 300ns. CB = capacitance of one bus line in pF SCL and SDA external pull-up voltage, VIO, is 3.13V < VIO < 5.5V. .
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LTC2978 TiMing DiagraM
SDA tf SCL tHD(STA) START CONDITION tHD(DAT) tHIGH tSU(STA) REPEATED START CONDITION tSU(STO)
2978 TD
tLOW
tr
tSU(DAT)
tf
tHD(SDA)
tSP
tr
tBUF
STOP CONDITION
START CONDITION
Typical perForMance characTerisTics
Reference Voltage vs Temperature
1.2355 REFERENCE OUTPUT VOLTAGE (V) 1.2350 1.2345 1.2340 ERROR (C) 1.2335 1.2330 1.2325 1.2320 1.2315 1.2310 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G01
Temperature Sensor Error vs Temperature
1.6 1.4 1.2 ERROR (%) 1.0 0.8 0.6 0.4 0.2 0.035 0.030 0.025 0.020 0.015 0.010 0.005
ADC Total Unadjusted Error vs Temperature
ADC VIN = 1.8V
THREE TYPICAL PARTS
0 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G02
0 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G03
ADC Zero Code Center Offset Voltage vs Temperature
0 -20 -40 ERROR (LSBs) -60 VOS (V) -80 -100 -120 -140 -160 -180 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G04
ADC-INL
3.0 2.5 2.0 ERROR (LSBs) 1.5 1.0 0.5 0 122V/LSB 0.8 0.6 0.4 0.2 0
ADC-DNL
122V/LSB
VOLTAGE SENSE MODE
-0.2 -0.4 -0.6 -0.8
-0.5 -1.0 -1.5 -0.2 0.8 1.8 2.8 3.8 4.8 INPUT VOLTAGE (V) 5.8
2978 G05
-1.0 -0.2
0.8
1.8 2.8 3.8 4.8 INPUT VOLTAGE (V)
5.8
2978 G06
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LTC2978 Typical perForMance characTerisTics
0 -20 REJECTION (dB) REJECTION (dB) -40 -60 -80
ADC Rejection vs Frequency at VIN
0 -20
ADC Rejection vs Frequency at VIN (Zoom)
0 -20 REJECTION (dB) -40 -60 -80
ADC Rejection vs Frequency at VIN (Current Sense Mode)
-40 -60 -80
-100 -120
-100 -120
-100 -120
0
12500
25000 37500 50000 FREQUENCY (Hz)
62500
2978 G07
0
3125
6250 9375 FREQUENCY (Hz)
12500
2978 G08
0
12500
25000 37500 50000 FREQUENCY (Hz)
62500
2978 G09
0 -20 REJECTION (dB) -40 -60 -80
ADC Rejection vs Frequency at VIN (Current Sense Mode, Zoom)
ADC Noise Histogram
1200 1000 NUMBER OF READINGS 800 600 400 200 0 -20 ERROR (%) VIN = 0V HIGH RESOLUTION MODE 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -10 0 10 READ_VOUT (V) 20
2978 G11
Voltage Supervisor Total Unadjusted Error vs Temperature
VIN = 0.8V HIGH RESOLUTION MODE
-100 -120
0
3125
6250 9375 FREQUENCY (Hz)
12500
2978 G10
-0.40 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G12
Input Sampling Current vs Differential Input Voltage
9 DIFFERENTIAL INPUT CURRENT (nA) 8 INPUT SAMPLING CURRENT (A) 7 6 5 4 3 2 1 0 0 1 2 3 4 INPUT VOLTAGE (V) 5 6
2978 G13
ADC High Resolution Mode Differential Input Current
90 80 OUTPUT VOLTAGE (V) 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 180 DIFFERENTIAL INPUT VOLTAGE (mV)
2978 G14
Voltage Buffered IDAC Full-Scale Output Voltage vs Temperature
2.698 2.696 2.694 2.692 2.690 2.688 2.686 2.684 2.682 2.680 2.678 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G15
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LTC2978 Typical perForMance characTerisTics
Voltage Buffered IDAC Offset Voltage vs Temperature
2.5 2.3 2.1 OFFSET ERROR (mV) 1.9 ERROR (LSBs) 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G16
Voltage Buffered IDAC-INL
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 200 600 400 DAC CODE 800 1000
2978 G17
Voltage Buffered IDAC DNL
1.0 0.8 0.6 0.4 ERROR (LSBs) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 200 600 400 DAC CODE 800 1000
2978 G18
Voltage Buffered IDAC Load Regulation (Sourcing)
2.698 2.696 2.694 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.692 2.690 2.688 2.686 2.684 2.682 2.680 2.678 -40C 25C 85C 0.1038 0.1036
IDAC Voltage Buffer Load Regulation (Sinking)
9.00 SHORT-CIRCUIT CURRENT (mA) 2 8.95 8.90 8.85 8.80 8.75
IDAC Voltage Buffer Short-Circuit Current vs Temperature
85C 0.1034 0.1032 0.1030 0.1028 0.1026 -40C 25C
0 -0.25 -0.5 -0.75 -1 -1.25 -1.50 1.75 CURRENT (mA)
-2
0
0.25 0.5 0.75 1 1.25 1.5 1.75 CURRENT (mA)
8.70 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G21
2978 G19
2978 G20
IDAC Voltage Buffer Transient Response to 1LSB DAC Code Change
CODE `h200
IDAC Voltage Buffer Soft Connect Transient Response when Transitioning from Hi-Z State to ON State
IDAC Voltage Buffer Soft Connect Transient Response when Transitioning from ON State to Hi-Z State
500V/DIV CODE `h1FF
HI-Z 10mV/DIV CONNECTED 10mV/DIV CONNECTED
HI-Z
2s/DIV
2978 G22
500s/DIV 100k SERIES RESISTANCE ON CODE: `h1FF
2978 G23
500s/DIV 100k SERIES RESISTANCE ON CODE: `h1FF
2978 G24
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0
LTC2978 Typical perForMance characTerisTics
VDD33 Regulator Output Voltage vs Temperature
3.275 3.270 VDD33 OUTPUT VOLTAGE (V) 3.265 VDD33 (ppm) 3.260 3.255 3.250 3.245 3.240 3.235 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G25
VDD33 Regulator Line Regulation
400 300 200 100 0 -100 -200 -300 -400 -500 4.5 6 7.5 9 10.5 VPWR (V) 12 13.5 15 -40C SHORT-CIRCUIT CURRENT (mA) 85C 25C -86 -88 -90 -92 -94 -96 -98
VDD33 Regulator Short-Circuit Current vs Temperature
-100 -102 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G27
2978 G26
Supply Current vs Supply Voltage
10.5 10.4 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10.3 10.2 10.1 10.0 9.9 9.8 3 3.1 3.2 3.3 VDD33 (V)
2978 G28
Supply Current vs Temperature
CHARGE PUMP OUTUPT HIGH VOLTAGE (V) 10.16 10.14 10.12 10.10 10.08 10.06 10.04 VPWR = 12V 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5
VOUT_EN[3:0] and VIN_EN Output High Voltage vs Load Current
85C 25C -40C
VPWR = VDD33
3.4
3.5
3.6
10.02 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C)
2978 G29
0
1
2 3 4 5 CURRENT SOURCING (A)
6
7
2978 G30
Voltage Buffered IDAC Output Impedance vs Frequency
1000 1.4 1.2 1.0 0.8 0.6 0.4 0.1 0.2 0.1 10 1 FREQUENCY (kHz) 100 1000
2978 G31
VOUT_EN[3:0] and VIN_EN VOL vs Current
0.6 0.5 0.4 VOLTS (V) 85C 25C -40C 0.3 0.2
VOUT_EN[7:4] VOL vs Current
OUTPUT IMPEDANCE ( )
100
VOLTS (V)
10
85C 25C -40C
1
0.1 0
0.01 0.01
0
0
2
4
8 6 ISINK (mA)
10
12
2978 G32
0
4
8
12 16 ISINK (mA)
20
24
2978 G33
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LTC2978 Typical perForMance characTerisTics
PWRGD and FAULTBzn VOL vs Current
1.2 1.0 0.8 VOLTS (V) VOLTS (V) 0.6 0.4 0.2 0 85C 25C -40C 0 2 4 6 8 ISINK (mA) 10 12
2978 G34
ALERTB VOL vs Current
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 8 6 ISINK (mA) 10 12
2978 G35
85C 25C -40C
pin FuncTions
PIN NAME VSENSEM6 VSENSEP7 VSENSEM7 VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 VIN_EN DNC VIN_SNS VPWR VDD33 VDD33 VDD25 WP PWRGD SHARE_CLK WDI/RESET PIN NUMBER PIN TYPE 1* In 2* In 3* In 4 Out 5 Out 6 Out 7 Out 8 Out 9 Out 10 Out 11 Out 12 0ut 13 Do Not Connect 14 In 15 16 17 18 19 20 21 22 In In/Out In In/Out In Out In/Out In DESCRIPTION DC/DC Converter Differential (-) Output Voltage-6 Sensing Pin DC/DC Converter Differential (+) Output Voltage or Current-7 Sensing Pin DC/DC Converter Differential (-) Output Voltage or Current-7 Sensing Pin DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled Up to 12V by 5A DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled Up to 12V by 5A DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled Up to 12V by 5A DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled Up to 12V by 5A DC/DC Converter Open-Drain Pull-Down Output-4 DC/DC Converter Open-Drain Pull-Down Output-5 DC/DC Converter Open-Drain Pull-Down Output-6 DC/DC Converter Open-Drain Pull-Down Output-7 DC/DC Converter VIN ENABLE Pin. Output High Voltage Optionally Pulled Up to 12V by 5A Do Not Connect to This Pin VIN SENSE Input. This Voltage is Compared Against the VIN On and Off Voltage Thresholds in Order to Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters VPWR Serves as the Unregulated Power Supply Input to the Chip (4.5V to 15V). If a 4.5V to 15V Supply Voltage is Unavailable, Short VPWR to VDD33 and Power the Chip Directly from a 3.3V Supply If Shorted to VPWR, it Serves as 3.13V to 3.47V Supply Input Pin. Otherwise it is a 3.3V Internally Regulated Voltage Output (Use 100nF Decoupling Capacitor to GND) Input for Internal 2.5V Sub-Regulator. Short This Pin to Pin 16 2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1F Capacitor Digital Input. Write-Protect Input Pin, Active High Power Good Open-Drain Output. Indicates When Outputs are Power Good. Can be Used as System Power-On Reset Bidirectional Clock Sharing Pin. Connect a 5.49k Pull-Up Resistor to VDD33 Watchdog Timer Interrupt and Chip Reset Input. Connect a 10k Pull-Up Resistor to VDD33. Rising Edge Resets Watchdog Counter. Holding This Pin Low for More Than tRESETB Resets the Chip
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LTC2978 pin FuncTions
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-00. Connect a 10k Pull-Up Resistor to VDD33 FAULTB01 24 In/Out Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-01. Connect a 10k Pull-Up Resistor to VDD33 FAULTB10 25 In/Out Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-10. Connect a 10k Pull-Up Resistor to VDD33 FAULTB11 26 In/Out Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-11. Connect a 10k Pull-Up Resistor to VDD33 SDA 27 In/Out PMBus Bidirectional Serial Data Pin SCL 28 In PMBus Serial Clock Input Pin (400kHz Maximum) ALERTB 29 Out Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation CONTROL0 30 In Control Pin 0 Input CONTROL1 31 In Control Pin 1 Input ASEL0 32 In Ternary Address Select Pin 0 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States ASEL1 33 In Ternary Address Select Pin 1 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States REFP 34 Out Reference Voltage Output. Needs 0.1F Decoupling Capacitor to REFM REFM 35 Out Reference Return Pin. Needs 0.1F Decoupling Capacitor to REFP . VSENSEP0 36* In DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin VSENSEM0 37* In DC/DC Converter Differential (-) Output Voltage-0 Sensing Pin VDACM0 38 Out Voltage Buffered IDAC0 Return. Connect to Channel 0 DC/DC Converter's GND Sense or Return to GND VDACP0 39 Out Voltage Buffered IDAC0 Output VDACP1 40 Out Voltage Buffered IDAC1 Output VDACM1 41 Out Voltage Buffered IDAC1 Return. Connect to Channel 1 DC/DC Converter's GND Sense or Return to GND VSENSEP1 42* In DC/DC Converter Differential (+) Output Voltage or Current-1 Sensing Pins VSENSEM1 43* In DC/DC Converter Differential (-) Output Voltage or Current-1 Sensing Pins VDACP2 44 Out Voltage Buffered IDAC2 Output VDACM2 45 Out Voltage Buffered IDAC2 Return. Connect to Channel 2 DC/DC Converter's GND Sense or Return to GND VSENSEP2 46* In DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin VSENSEM2 47* In DC/DC Converter Differential (-) Output Voltage-2 Sensing Pin VSENSEP3 48* In DC/DC Converter Differential (+) Output Voltage or Current-3 Sensing Pins VSENSEM3 49* In DC/DC Converter Differential (-) Output Voltage or Current-3 Sensing Pins VDACP3 50 Out Voltage Buffered IDAC3 Output VDACM3 51 Out Voltage Buffered IDAC3 Return. Connect to Channel 3 DC/DC Converter's GND Sense or Return to GND VSENSEP4 52* In DC/DC Converter Differential (+) Output Voltage-4 Sensing Pin VSENSEM4 53* In DC/DC Converter Differential (-) Output Voltage-4 Sensing Pin VDACM4 54 Out Voltage Buffered IDAC4 Return. Connect to Channel 4 DC/DC Converter's GND Sense or Return to GND VDACP4 55 Out Voltage Buffered IDAC4 Output VDACP5 56 Out Voltage Buffered IDAC5 Output VDACM5 57 Out Voltage Buffered IDAC5 Return. Connect to Channel 5 DC/DC Converter's GND Sense or Return to GND VDACM6 58 Out Voltage Buffered IDAC6 Return. Connect to Channel 6 DC/DC Converter's GND Sense or Return to GND VDACP6 59 Out Voltage Buffered IDAC6 Output VDACP7 60 Out Voltage Buffered IDAC7 Output VDACM7 61 Out Voltage Buffered IDAC7 Return. Connect to Channel 7 DC/DC Converter's GND Sense or Return to GND VSENSEP5 62* In DC/DC Converter Differential (+) Output Voltage or Current-5 Sensing Pins VSENSEM5 63* In DC/DC Converter Differential (-) Output Voltage or Current-5 Sensing Pins VSENSEP6 64* In DC/DC Converter Differential (+) Output Voltage-6 Sensing Pin GND 65 Ground Exposed Pad, Must be Soldered to PCB *Any unused VSENSEPn or VSENSEMn pins must be tied to GND. FAULTB00 23 In/Out
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LTC2978 block DiagraM
VPWR 15 VDD33 16 VDD33 17 VDD25 18 VIN_SNS 14 3R R GND 65 2.5V REGULATOR VIN VOUT VSENSEM0 VSENSEP0 VSENSEM1 VSENSEP1 VSENSEM2 VSENSEP2 VSENSEM3 VSENSEP3 INTERNAL TEMP SENSOR VSENSEP4 VSENSEM5 VSENSEP5 VSENSEM6 VSENSEP6 VSENSEM7 VSENSEP7 36 VSENSEP0 37 VSENSEM0 42 VSENSEP1 43 VSENSEM1 46 VSENSEP2 47 VSENSEM2 3.3V REGULATOR VIN VOUT VDD
MUX
CMP0
+ -
15-BIT ADC IDAC0 10 BITS
ADC CLOCKS VDD REFP 34 REFM 35 REFERENCE 1.232V (TYP)
SCL 28 SDA 27 ALERTB 29 ASEL0 32 ASEL1 33 WP 19 CONTROL0 30 CONTROL1 31 WDI/RESET 22 FAULTB00 23 FAULTB01 24 FAULTB10 25 FAULTB11 26 PWRGD 20 SHARE_CLK 21 CONTROLLER PMBus ALGORITHM FAULT PROCESSOR WATCHDOG SEQUENCER PMBus INTERFACE (400kHz I2C COMPATIBLE)
NONVOLATILE MEMORY EEPROM RAM ADC_RESULTS MONITOR LIMITS SERVO TARGETS
+ - + -
VSENSEM4
+ -
10-BIT VDAC
48 VSENSEP3 49 VSENSEM3 52 VSENSEP4 53 VSENSEM4 62 VSENSEP5 63 VSENSEM5 64 VSENSEP6 1 VSENSEM6 2 VSENSEP7 3 VSENSEM7 39 VDACP0 40 VDACP1 44 VDACP2 50 VDACP3 55 VDACP4 56 VDACP5 59 VDACP6 60 VDACP7 38 VDACM0 41 VDACM1 45 VDACM2 51 VDACM3 54 VDACM4 57 VDACM5 58 VDACM6 61 VDACM7 4 VOUT_EN0 OUTPUT CONFIG 5 VOUT_EN1 6 VOUT_EN2 7 VOUT_EN3 12 VIN_EN 8 VOUT_EN4 OPEN-DRAIN OUTPUT 9 VOUT_EN5 10 VOUT_EN6 11 VOUT_EN7
2978 BD
+SC + - -
VBUF0
CMP0
OSCILLATOR VDD UVLO
CLOCK GENERATION
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LTC2978 operaTion
OPERATION OVERVIEW The LTC2978 is a PMBus programmable power supply controller, monitor, sequencer and voltage supervisor that can perform the following operations:
n n n
Store command register contents to EEPROM through PMBus programming. Restore EEPROM contents through PMBus programming or on POR. Report the DC/DC converter output voltage status through the PMBus interface and the power good output. Generate interrupt requests by asserting the ALERTB pin in response to supported PMBus faults. Shut down multiple DC/DC converters in response to a fault through the FAULTBz0 and FAULTBz1 pins. Synchronize sequencing delays or shutdown for multiple devices using the SHARE_CLK pin. Software and hardware write protect the command registers. Disable the input voltage to the supervised DC/DC converters in response to output voltage OV and UV faults. Log telemetry and status data to EEPROM in response to a faulted-off condition Supervise an external microcontroller's activity for a stalled condition with a programmable watchdog timer and reset it if necessary. Prevent a DC/DC converter from re-entering the ON state after a power cycle until a programmable interval (MFR_RESTART_DELAY) has elapsed and its output has decayed below a programmable threshold voltage (MFR_VOUT_DISCHARGE_THRESHOLD). Record minimum and maximum observed values of input voltage, output voltages and temperature.
n
Accept PMBus compatible programming commands. Provide DC/DC converter input voltage and output voltage/current read back through the PMBus interface. Control the output of modules that set voltage with a trim pin or modules that set the output voltage using an external resistor feedback network. Sequence the start-up of DC/DC converters via PMBus programming and the CONTROL input pins. Trim the DC/DC converter output voltage (typically in 0.1% steps), in closed-loop servo operating mode, through PMBus programming. Margin the DC/DC converter output voltage to PMBus programmed limits (typically 10%). Allow the user to trim or margin the DC/DC converter output voltage in a manual operating mode by providing direct access to the margin DAC. Supervise the DC/DC converter output voltage, input voltage, and the LTC2978 die temperature for overvalue/undervalue conditions with respect to PMBus programmed limits and generate appropriate faults and warnings. Respond to a fault condition by either continuing operation indefinitely, latching off after a programmable de-glitch period or latching off immediately. A retry mode may be used to automatically recover from a latched-off condition. Stop trimming the DC/DC converter output voltage after it reached the initial margin or nominal target. Optionally allows servo to resume if target drifts outside of VOUT warning limits.
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
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LTC2978 operaTion
PMBus SERIAL DIGITAL INTERFACE The LTC2978 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC2978 is a slave device. The master can communicate with the LTC2978 using the following formats:
n n
Figures 1-10 illustrate the aforementioned SMBus protocols. All transactions support PEC (parity error check) and GCP (group command protocol). The Block Read supports 256 bytes of returned data. For this reason, the PMBus timeout may be extended using the Mfr_config_all_ longer_pmbus_timeout setting. The LTC2978 will not acknowledge any PMBus command if it is still busy with a STORE_USER_ALL, RESTORE_USER_ ALL, MFR_CONFIG or if fault log data is being written to the EEPROM. Status_word_busy will also be set. Slave Address The LTC2978 can be configured to respond to one of nine addresses for a given MFR_I2C_BASE_ADDRESS value (the factory default value for this register is 7'h5C). In addition, the LTC2978 will always respond to its global address and the PMBus Alert Response address regardless of the state of the address select pins. By connecting each of the address inputs to VDD33, GND, or by floating them, the user determines the slave address as shown in Table 1.
Master transmitter, slave receiver Master receiver, slave transmitter Write Byte, Write Word, Send Byte Read Byte, Read Word, Block Read Alert Response Address
The following SMBus protocols are supported:
n n n
Table 1. LTC2978 Address Look-Up Table
DESCRIPTION Alert Response Global 0* 1 2 3 4 5 6 7 8 HEX DEVICE ADDRESS 7'h 0C 5B 5C 5D 5E 5F 60 61 62 63 64 8'h 19 B6 B8 BA BC BE C0 C2 C4 C6 C8 6 0 1 1 1 1 1 1 1 1 1 1 5 0 0 0 0 0 0 1 1 1 1 1 4 0 1 1 1 1 1 0 0 0 0 0 BINARY DEVICE ADDRESS 3 1 1 1 1 1 1 0 0 0 0 0 2 1 0 1 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 R/W 1 0 0 0 0 0 0 0 0 0 0 ADDRESS PINS ASEL1 X X L L L NC NC NC H H H ASEL0 X X L NC H L NC H L NC H
H = Tie to VDD33, NC = No Connect, Open or Float, L = Tie to GND, X = Don't Care *MFR_I2C_BASE_ADDRESS = 7'h5C (Factory Default)
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LTC2978 operaTion
1 S 7 1 1 8 1 8 DATA BYTE 1 A 1 P
2978 F01
SLAVE ADDRESS Wr A COMMAND CODE A
Figure 1. Write Byte Protocol
1 S 7 1 1 8 1 8 DATA BYTE LOW 1 A 8 DATA BYTE HIGH 1 A 1 P
2978 F02
SLAVE ADDRESS Wr A COMMAND CODE A
Figure 2. Write Word Protocol
1 S 7 1 1 8 1 8 DATA BYTE 1 A 8 PEC 1 A 1 P
2978 F03
SLAVE ADDRESS Wr A COMMAND CODE A
Figure 3. Write Byte Protocol with PEC
1 S 7 1 1 8 1 8 DATA BYTE LOW 1 A 8 DATA BYTE HIGH 1 A 8 PEC 1 A 1 P
2978 F04
SLAVE ADDRESS Wr A COMMAND CODE A
Figure 4. Write Word Protocol with PEC
1 S 7 1 1 8 DATA BYTE 1 A 1 P
2978 F05
SLAVE ADDRESS Wr A
Figure 5. Send Byte Protocol
1 S 7 1 1 8 DATA BYTE 1 A 8 PEC 1 A 1 P
2978 F06
SLAVE ADDRESS Wr A
Figure 6. Send Byte Protocol with PEC
1 S 7 1 1 8 1 1 S 7 1 1 8 DATA BYTE LOW 1 A 8 1 1 P
SLAVE ADDRESS Wr A COMMAND CODE A
SLAVE ADDRESS Rd A
DATA BYTE HIGH A
1 2978 F07
Figure 7. Read Word Protocol
1 S 7 1 1 8 1 1 S 7 1 1 8 DATA BYTE LOW 1 A 8 1 8 PEC 1 A 1 P
SLAVE ADDRESS Wr A COMMAND CODE A
SLAVE ADDRESS Rd A
DATA BYTE HIGH A
1 2978 F08
Figure 8. Read Word Protocol with PEC
1 S 7 1 1 8 1 1 S 8 1 1 8 DATA BYTE 1 A 1 P
SLAVE ADDRESS Wr A COMMAND CODE A
SLAVE ADDRESS Rd A
1 2978 F09
Figure 9. Read Byte Protocol
1 S 7 1 1 8 1 1 S 8 1 1 8 DATA BYTE 1 A PEC 1 A 1 P
SLAVE ADDRESS Wr A COMMAND CODE A
SLAVE ADDRESS Rd A
1 2978 F10
Figure 10. Read Byte Protocol with PEC
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LTC2978 operaTion
REGISTER COMMAND SET
Summary
COMMAND FUNCTION PAGE OPERATION ON_OFF_CONFIG CLEAR_FAULTS WRITE_PROTECT STORE_USER_ALL RESTORE_USER_ALL CAPABILITY Operating mode control. CONTROL pin and PMBus bus on/off command setting. CLEAR_FAULTS is used to clear any fault bits that have been set. Provides protection against accidental changes. Store entire operating memory to EEPROM. Restore entire operating memory from EEPROM. The CAPABILITY command provides a way for a host system to determine the capabilities of the PMBus device. Output voltage format control. Servo DC/DC converter output voltage value setting. The VOUT_MAX command sets an upper limit on the output voltage, in volts, the unit can command regardless of any other commands or combinations. Margin high DC/DC converter output voltage limit setting. Margin low DC/DC converter output voltage limit setting. The VIN_ON command sets the input voltage, in volts, at which the unit should start power conversion. The VIN_OFF command sets the input voltage, in volts, at which the unit should stop power conversion. Overvoltage DC/DC converter fault limit setting. The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. Overvoltage DC/DC converter warning limit setting. Undervoltage DC/DC converter warning limit setting. DESCRIPTION R/W R/W R/W R/W W R/W W W R DATA NV LENGTH COMMAND MEMORY (BITS) BYTE VALUE TYPE 8 8 8 0 8 0 0 8 `h00 `h01 `h02 `h03 `h10 `h15 `h16 `h19 ROM EEPROM EEPROM EEPROM DEFAULT VALUE `h00 `h00 `h12 NA `h00 NA NA `hE0 PAGED ? N Y Y Y N N N N
VOUT_MODE VOUT_COMMAND VOUT_MAX
R R/W R/W
8 16 16
`h20 `h21 `h24
ROM EEPROM EEPROM
`h13 `h2000 `h8000
Y Y Y
VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VIN_ON
R/W R/W R/W
16 16 16
`h25 `h26 `h35
EEPROM EEPROM EEPROM
`h219A `h1E66 `hD280
Y Y N
VIN_OFF
R/W
16
`h36
EEPROM
`hD240
N
VOUT_OV_FAULT_LIMIT VOUT_OV_FAULT_RESPONSE
R/W R/W
16 8
`h40 `h41
EEPROM EEPROM
`h2333 `h80
Y Y
VOUT_OV_WARN_LIMIT VOUT_UV_WARN_LIMIT
R/W R/W
16 16
`h42 `h43
EEPROM EEPROM
`h2266 `h1D9A
Y Y
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LTC2978 operaTion
Summary
COMMAND FUNCTION VOUT_UV_FAULT_LIMIT DESCRIPTION R/W DATA NV LENGTH COMMAND MEMORY (BITS) BYTE VALUE TYPE 16 `h44 EEPROM DEFAULT VALUE `h1CCD PAGED ? Y
Undervoltage DC/DC converter fault limit R/W setting. This limit is also used to determine if Ton_max_fault has been met and the unit is on. The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an undervoltage fault. Overtemperature fault limit setting. The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an overtemperature fault. Overtemperature warning limit setting. Undertemperature warn limit setting. Undertemperature fault limit setting. The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an undertemperature fault. Input supply overvoltage fault limit setting. R/W
VOUT_UV_FAULT_RESPONSE
8
`h45
EEPROM
`h7F
Y
OT_FAULT_LIMIT OT_FAULT_RESPONSE
R/W R/W
16 8
`h4F `h50
EEPROM EEPROM
`hEAA8 `hB8
N N
OT_WARN_LIMIT UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE
R/W R/W R/W R/W
16 16 16 8
`h51 `h52 `h53 `h54
EEPROM EEPROM EEPROM EEPROM
`hEA58 `h8000 `hCD80 `hB8
N N N N
VIN_OV_FAULT_LIMIT VIN_OV_FAULT_RESPONSE
R/W
16 8
`h55 `h56
EEPROM EEPROM
`hD3C0 `h80
N N
The VIN_OV_FAULT_RESPONSE command R/W instructs the device on what action to take in response to an input overvoltage fault. Overvoltage input supply warning limit setting. Undervoltage input supply warning limit setting. Undervoltage input supply fault limit setting. R/W R/W R/W
VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE
16 16 16 8
`h57 `h58 `h59 `h5A
EEPROM EEPROM EEPROM EEPROM
`hD380 `h8000 `h8000 `h00
N N N N
The VIN_UV_FAULT_RESPONSE command R/W instructs the device on what action to take in response to an input undervoltage fault. Output voltage at or above which a power good should be asserted. Output voltage at or below which a power good should be deasserted. Time, in ms, from CONTROL and/or Operation on to VOUT_EN on. Time, in ms, from when the output starts to rise until the LTC2978 optionally softconnects its voltage-buffered current DAC and begins to servo the output voltage to the desired value. Maximum time, in ms, from VOUT_EN on assertion that an UV condition will be tolerated before a TON_MAX_FAULT condition results. Specifies response to a TON_MAX_FAULT event. R/W R/W R/W R/W
POWER_GOOD_ON POWER_GOOD_OFF TON_DELAY TON_RISE
16 16 16 16
`h5E `h5F `h60 `h61
EEPROM EEPROM EEPROM EEPROM
`h1EB8 `h1E14 `hBA00 `hD280
Y Y Y Y
TON_MAX_FAULT_LIMIT
R/W
16
`h62
EEPROM
`hD3C0
Y
TON_MAX_FAULT_RESPONSE
R/W
8
`h63
EEPROM
`hB8
Y
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LTC2978 operaTion
Summary
COMMAND FUNCTION TOFF_DELAY STATUS_BYTE STATUS_WORD DESCRIPTION Time, in ms, from CONTROL and/or Operation off to VOUT_EN off. Fault status reporting. The STATUS_WORD command returns two bytes of information with a summary of the unit's fault condition. Voltage fault status reporting. The STATUS_INPUT command returns one byte with status on VIN_SNS. The STATUS_TEMPERATURE command returns one byte with status information on temperature. The STATUS_CML command returns one byte with status information on communication and memory. The STATUS_MFR_SPECIFIC command returns one byte with the manufacturer specific status information. Input supply voltage read back. DC/DC converter output voltage read back. Internal junction temperature read back. Read the supported PMBus revision (1.1). Manufacturer configuration bits that are channel specific. Manufacturer configuration bits that are common to all pages. Manufacturer configuration that determines which channel faults are propagated to FAULTBz0 where z = 0 for channels 0-3, and z=1 for channels 4-7. Manufacturer configuration that determines which channel faults are propagated to FAULTBz1. Maps PWRGD status to the PWRGD pin. Determines response to FAULTB00 pin being asserted low. Determines response to FAULTB01 pin being asserted low. Determines response to FAULTB10 pin being asserted low. Determines response to FAULTB11 pin being asserted low. Determines the response of the VIN_EN pin to a VOUT_OV_FAULT R/W R/W R R DATA NV LENGTH COMMAND MEMORY (BITS) BYTE VALUE TYPE 16 8 16 `h64 `h78 `h79 EEPROM DEFAULT VALUE `hBA00 NA NA PAGED ? Y Y Y
STATUS_VOUT STATUS_INPUT STATUS_TEMPERATURE
R R R
8 8 8
`h7A `h7C `h7D
NA NA NA
Y N N
STATUS_CML
R
8
`h7E
NA
N
STATUS_MFR_SPECIFIC
R
8
`h80
NA
Y
READ_VIN READ_VOUT READ_TEMPERATURE_1 PMBUS_REVISION MFR_CONFIG MFR_CONFIG_ALL MFR_FAULTBz0_PROPAGATE
R R R R R/W R/W R/W
16 16 16 8 16 8 8
`h88 `h8B `h8D `h98 `hD0 `hD1 `hD2 ROM EEPROM EEPROM EEPROM
NA NA NA `h11 `h0080 `h7B `h00
N Y N N Y N Y
MFR_FAULTBz1_PROPAGATE
R/W
8
`hD3
EEPROM
`h00
Y
MFR_PWRGD_EN MFR_FAULTB00_RESPONSE MFR_FAULTB01_RESPONSE MFR_FAULTB10_RESPONSE MFR_FAULTB11_RESPONSE MFR_VINEN_OV_FAULT_RESPONSE
R/W R/W R/W R/W R/W R/W
16 8 8 8 8 8
`hD4 `hD5 `hD6 `hD7 `hD8 `hD9
EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM
`h0000 `h00 `h00 `h00 `h00 `h00
N N N N N N
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0
LTC2978 operaTion
Summary
COMMAND FUNCTION MFR_VINEN_UV_FAULT_RESPONSE MFR_RETRY_DELAY MFR_RESTART_DELAY MFR_VOUT_PEAK MFR_VIN_PEAK MFR_TEMPERATURE_PEAK MFR_DAC DESCRIPTION Determines the response of the VIN_EN pin to a VOUT_UV_FAULT Sets retry interval during retry mode. Sets delay from actual CONTROL active edge to virtual CONTROL active edge. Returns the maximum measured value of VOUT . Returns the maximum measured value of VIN_SNS. Returns the maximum measured value of temperature. Manufacturer register that contains the code of the 10-bit voltage-buffered current DAC. Determines power good output assertion delay. First watchdog timer interval. Watchdog timer interval. Selects which channels respond to global page commands. Returns values detected and driven onto digital I/O pads. This register determines the base value of the I2C address byte. This register contains the manufacturer code for identifying the LTC2978. These registers contain customer dependent codes that identify the factory programmed user configuration stored in EEPROM. Coefficient used to multiply VOUT_ COMMAND in order to determine VOUT OFF threshold voltage. Command a transfer of the fault log from RAM to EEPROM. This causes the part to behave as if a channel has faulted off. Command a transfer of the fault log previously stored in EEPROM back to RAM. Initialize the EEPROM block reserved for fault logging and clear any previous fault logging locks. This command returns one byte with status information on fault logging. Fault log. Accessed using a block read. Returns data in the form last in first out. R/W R/W R/W R/W R R R R/W DATA NV LENGTH COMMAND MEMORY (BITS) BYTE VALUE TYPE 8 16 16 16 16 16 16 `hDA `hDB `hDC `hDD `hDE `hDF `hE0 EEPROM EEPROM EEPROM EEPROM DEFAULT VALUE `h00 `hF320 `hFB20 NA NA NA `h0000 PAGED ? N N N Y N N Y
MFR_POWERGOOD_ASSERTION_DELAY MFR_WATCHDOG_T_FIRST MFR_WATCHDOG_T MFR_PAGE_FF_MASK MFR_PADS MFR_I2C_BASE_ADDRESS MFR_SPECIAL_ID MFR_SPECIAL_LOT
R/W R/W R/W R/W R R/W R R/W
16 16 16 8 16 8 16 8
`hE1 `hE2 `hE3 `hE4 `hE5 `hE6 `hE7 `hE8
EEPROM EEPROM EEPROM EEPROM
`hEB20 `h8000 `h8000 `hFF N/A
N N N N N N N Y
EEPROM EEPROM EEPROM
`h5C `h0121 Contact the Factory `hC200
MFR_VOUT_DISCHARGE_THRESHOLD
R/W
16
`hE9
EEPROM
Y
MFR_FAULT_LOG_STORE
W
0
`hEA
NA
N
MFR_FAULT_LOG_RESTORE
W
0
`hEB
NA
N
MFR_FAULT_LOG_CLEAR
W
0
`hEC
NA
N
MFR_FAULT_LOG_STATUS MFR_FAULT_LOG
R R
8 2048
`hED `hEE
EEPROM EEPROM
NA NA
N N
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LTC2978 operaTion
Summary
COMMAND FUNCTION MFR_COMMON MFR_SPARE_0 MFR_SPARE_2 MFR_VOUT_MIN MFR_VIN_MIN MFR_TEMPERATURE_MIN DESCRIPTION Contains manufacturer status bits that are common across multiple LTC chips. Scratchpad register. Paged scratchpad register. Returns the minimum measured value of VOUT. Returns the minimum measured value of VIN_SNS. Returns the minimum measured junction temperature value. R/W R R/W R/W R R R DATA NV LENGTH COMMAND MEMORY (BITS) BYTE VALUE TYPE 8 16 16 16 16 16 `hEF `hF7 `hF9 `hFB `hFC `hFD EEPROM EEPROM DEFAULT VALUE NA `h0000 `h0000 NA NA NA PAGED ? N N Y Y N N
DETAILED PMBus COMMAND REGISTER DESCRIPTIONS PAGE The PAGE command provides the ability to configure, control and monitor multiple outputs on one unit. Setting PAGE = `hFF allows PMBus commands that support global page programming to be written simultaneously. The only commands that support PAGE = `hFF are OPERATION and ON_OFF_CONFIG. See MFR_PAGE_FF_ MASK for additional options. Reading any PMBus register with PAGE = `hFF returns unpredictable data and will trigger a CML fault.
PAGE Data Contents
BIT(S) SYMBOL PURPOSE b[7:0] Page Page operation. `h00: All PMBus commands address channel/page 0. `h01: All PMBus commands address channel/page 1. * * * `h07: All PMBus commands address channel/page 7. `hXX: All nonspecified values reserved. `hFF: PMBus commands that support this global PAGE write mode will be written simultaneously.
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LTC2978 operaTion
OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the CONTROLn pin and ON_OFF_ CONFIG. This command register responds to the global page command. The contents and functions of the data byte are shown in the following tables.
OPERATION Data Contents When On_Off_Config_Use_PMBus Enables Operation_Control
SYMBOL BITS Turn off immediately Turn on Margin Low (Ignore Faults and Warnings) Margin Low Margin High (Ignore Faults and Warnings Margin High FUNCTION Sequence off and margin to nominal Sequence off and Margin Low (Ignore Faults and Warnings) Sequence off and Margin Low Sequence off and Margin High (Ignore Faults and Warnings) Sequence off and Margin High Reserved Action Operation_control[1:0] b[7:6] 00 10 10 10 10 10 01 01 01 01 01 Operation_margin[1:0] b[5:4] XX 00 01 01 10 10 00 01 01 10 10 Operation_fault[1:0] b[3:2] XX XX 01 10 01 10 XX 01 10 01 10 Reserved (read only) b[1:0] 00 00 00 00 00 00 00 00 00 00 00
All remaining combinations
OPERATION Data Contents When On_Off_Config is Configured Such That OPERATION Command is Not Used to Command Channel On or Off
SYMBOL BITS Output at Nominal Margin Low (Ignore faults and Warnings) FUNCTION Margin Low Margin High (Ignore Faults and Warnings Margin High Reserved Action Operation_control[1:0] b[7:6] 00, 01 or 10 00, 01 or 10 00, 01 or 10 00, 01 or 10 00, 01 or 10 Operation_margin[1:0] b[5:4] 00 01 01 10 10 Operation_fault[1:0] b[3:2] XX 01 10 01 10 Reserved (read only) b[1:0] 00 00 00 00 00
All remaining combinations
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ON_OFF_CONFIG The ON_OFF_CONFIG command configures the combination of CONTROLn pin input and PMBus bus commands needed to turn the LTC2978 on/off, including the power-on behavior, as shown in the following table. This command register responds to the global page command.
ON_OFF_CONFIG Data Contents
BITS(S) SYMBOL b[7:5] Reserved b[4] On_off_config_controlled_on OPERATION Don't care. Always returns 0. Control default autonomous power-up operation. 0: Unit powers up regardless of the CONTROLn pin. Unit always powers up with sequencing. To turn unit on without sequencing, set TON_DELAY = 0. 1: Unit does not power up unless commanded by the CONTROLn pin and/or the OPERATION command on the serial bus. If On_off_config[3:2] = 00, the unit never powers up. Controls how the unit responds to commands received via the serial bus. 0: Unit ignores the Operation_control[1:0]. 1: Unit responds to Operation_control[1:0]. Depending on On_off_config_use_control, the unit may also require the CONTROLn pin to be asserted for the unit to start. Controls how unit responds to the CONTROLn pin. 0: Unit ignores the CONTROLn pin. 1: Unit requires the CONTROLn pin to be asserted to start the unit. Depending on On_off_config_use_ PMBus the OPERATION command may also be required to instruct the device to start. Not supported. Always returns 1. CONTROLn pin turn off action when commanding the unit to turn off 0: Use the programmed TOFF_DELAY. 1: Turn off the output and stop transferring energy as quickly as possible. The device does not sink current in order to decrease the output voltage fall time.
b[3]
On_off_config_use_pmbus
b[2]
On_off_config_use_control
b[1] b[0]
Reserved On_off_config_control_fast_off
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LTC2978 operaTion
CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any status faults that have been set. This command clears all bits in all unpaged status registers, and the paged status registers selected by the current PAGE setting. At the same time, the device negates (clears, releases) its contribution to ALERTB. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault condition is present after the fault status is cleared, the fault status bit shall be set again and the host notified by the usual means. Note: this command register does not respond to the global page command. WRITE_PROTECT The WRITE_PROTECT command provides protection against accidental programming of the LTC2978 command registers. All supported commands may have their parameters read, regardless of the WRITE_PROTECT setting.
WRITE_PROTECT Data Contents
BITS(S) SYMBOL b[7:0] Write_protect[7:0] OPERATION 8'b1000_0000: Disable all writes except to the WRITE_PROTECT, PAGE, and STORE_USER_ALL commands. 8'b0100_0000: Disable all writes except to the WRITE_PROTECT, PAGE, STORE_ USER_ALL, OPERATION, MFR_PAGE_ FF_MASK, and CLEAR_FAULTS. 8'b0000_0000: Enable writes to all commands. 8'bxxxx_xxxx: All other values reserved. b[4:0] Reserved
STORE_USER_ALL. No Data Contents. Accessing this command will store all operating memory commands with a corresponding EEPROM memory location. It is recommended that this command not be executed while a unit is enabled since all monitoring is suspended while the operating memory is transferred to EEPROM. RESTORE_USER_ALL. No Data Contents. Accessing this command will restore all commands from EEPROM Memory. It is recommend that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially stored in operating memory. CAPABILITY The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2978. This one byte command is read only.
CAPABILITY Data Contents
BITS(S) SYMBOL b[7] Capability_pec OPERATION Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate whether PEC is currently required. Hard coded to 1 indicating the maximum supported bus speed is 400kHz. Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response Protocol. X: Always returns 0.
b[6]
Capability_scl_max
b[5]
Capability_smb_alert
STORE_USER_ALL and RESTORE_USER_ALL STORE_USER_ALL, RESTORE_USER_ALL commands provide access to user nonvolatile EEPROM memory. Once a command is stored in EEPROM, it will be restored with explicit restore command or when the part emerges from power-on reset after power is applied. While either of these commands is being processed, the device will NACK I2C writes.
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LTC2978 operaTion
VOUT_MODE The data byte for the VOUT_MODE command is 8 bits that consists of a three bit format and a five bit exponent. The three bit format specifies PMBus linear mode for all output voltage related commands. The five bit exponent provides the exponent for the mantissa specified in the data word. The LTC2978 device sets the format at the time of manufacture. The five bit exponent is read only and is set to a value of -13 decimal. Output voltage related commands are calculated as follows except for odd numbered channels configured to measure current: Voltage = V[15:0] * 2N where Voltage is the parameter of interest in volts. V is a 16-bit unsigned binary integer for all voltages, (e.g. Margin_high[15:0]); N = Vout_mode_exponent, is a 5-bit two's complementary binary integer with a value hardwired to -13 decimal. Vout_mode_parameter is read only. Vout_mode_type is read only.
VOUT_MODE Data Contents
BIT(S) SYMBOL b[7:5] b[4:0] Vout_mode_type OPERATION Reports linear mode. Hard wired to 3'b000.
Output Voltage Related Commands VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_ HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT, VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and POWER_GOOD_OFF These commands use the same format and provide various servo, margining, and supervising limits for a channel's output voltage. When odd channels are configured to measure current, the OV_WARN_LIMIT, UV_WARN_LIMIT, OV_FAULT_LIMIT and UV_FAULT_LIMIT commands are not supported.
Data Contents
BIT(S) SYMBOL Vout_max[15:0], Vout_margin_high[15:0], Vout_margin_low[15:0], Vout_ov_fault_limit[15:0], Vout_ov_warn_limit[15:0], Vout_uv_warn_limit[15:0], Vout_uv_fault_limit[15:0], Power_good_on[15:0], Power_good_off[15:0] OPERATION These commands relate to output voltage. The data uses the linear mode format as defined by VOUT_MODE: V(Symbol) = Y * 2N where Y = b[15:0] is an unsigned integer and N = Vout_mode_ parameter is a 5-bit two's complement exponent that's hardwired to -13 decimal. Units: V b[15:0] Vout_command[15:0],
Vout_mode_parameter Linear mode exponent. 5-bit two's complement integer. Hardwired to `h13 (-13 decimal).
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Input Voltage Related Commands VIN_ON, VIN_OFF VIN_OV_FAULT_LIMIT, VIN_OV_ , WARN_LIMIT, VIN_UV_WARN_LIMIT and VIN_UV_ FAULT_LIMIT These commands use the same format and provide voltage supervising limits for VIN.
Data Contents
BIT(S) SYMBOL b[15:0] Vin_on[15:0], Vin_off[15:0], Vin_ov_fault_limit[15:0], Vin_ov_warn_limit[15:0], Vin_uv_warn_limit[15:0], Vin_uv_fault_limit[15:0] OPERATION These commands relate to input voltage. The data uses the linear format: V(Symbol) = Y * 2N where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: V.
TON_DELAY is the amount time in ms that elapses after the channel has been allowed on (usually due to CONTROLn pin or OPERATION command) until the channel enables the power supply. This delay is counted using SHARE_CLK only. TON_RISE is the amount of time in ms that elapses after the power supply has been enabled until the LTC2978's voltage buffered current DAC soft connects and servo's the output voltage to the desired level if Mfr_dac_mode = 2'b00. This delay is counted using SHARE_CLK only. TON_MAX_FAULT_LIMIT is the maximum amount of time that can elapse after the power supply has been enabled until the LTC2978 unmasks the VOUT_UV_FAULT_LIMIT threshold. (Note that a value of zero means there is no limit to how long the power supply can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only. TOFF_DELAY is the amount of time that elapses after the CONTROLn pin and/or OPERATION command is deasserted until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used.
Data Contents
BIT(S) SYMBOL OPERATION The data uses the linear format: T(Symbol) = Y * 2N b[15:0] Ton_delay[15:0], Ton_rise[15:0],
Temperature Related Commands OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT These commands provide supervising limits for temperature.
Data Contents
BIT(S) SYMBOL b[15:0] Ot_fault_limit[15:0], Ot_warn_limit[15:0], Ut_warn_limit[15:0], Ut_fault_limit[15:0] OPERATION The data uses the linear format: T(Symbol) = Y * 2N where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: C.
Ton_max_fault_limit[15:0], Where N = b[15:11] is a 5-bit two's complement integer and Toff_delay[15:0], Y = b[10:0] is an 11-bit two's complement integer The internal timers operate on a 10s internal clock. The SHARE_CLK pin may be used to synchronize the 10s timer. Delays are rounded to the nearest 10s Units: ms. Max value: 655ms
Timer Limits TON_DELAY TON_RISE, TON_MAX_FAULT_LIMIT and , TOFF_DELAY These commands share the same format and provide sequencing and timer fault and warning delays in ms.
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Fault Response for Voltages Measured by the High Speed Supervisor VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_ RESPONSE The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages are measured over a short period of time and may require a de-glitch period. Note that in addition to the response described by these commands, the LTC2978 will also:
Data Contents
BIT(S) SYMBOL b[7:6] Vout_ov_fault_response_action, Vout_uv_fault_response_action OPERATION Response action. 2'b00: The unit continues operation without interruption. 2'b01: The unit continues operating for the delay time specified by bits[2:0] in increments of Ts_vs. If the fault is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 2'b1X: The device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] Vout_ov_fault_response_retry, Vout_uv_fault_response_retry Response action: 3'b000: A zero value for the retry setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared. 3'b001-111: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay, until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] Vout_ov_fault_response_delay, Vout_uv_fault_response_delay This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this delay to de-glitch fast faults. 3'b000: The unit turns off immediately. 3'b001 - 3'b111: The unit turns off after b[2:0] samples at the sampling period of Ts_vs (12.2s typical).
* Set the appropriate bit(s) in the STATUS_BYTE * Set the appropriate bit(s) in the STATUS_WORD * Set the appropriate bit in the corresponding STATUS_ VOUT register, and * Notify the host by pulling the ALERTB pin low. Note: Odd numbered channels configured for high resolution ADC measurements will not respond to OV/UV faults or warnings.
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LTC2978 operaTion
Fault Response for Values Measured by the ADC OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_ RESPONSE The fault response documented here is for values that are measured by the ADC. These values are measured over a longer period of time and are not de-glitched. Note that in addition to the response described by these commands, the LTC2978 will also:
Data Contents
BIT(S) SYMBOL b[7:6] Ot_fault_response_action, Ut_fault_response_action, Vin_ov_fault_response_action, Vin_uv_fault_response_action b[5:3] Ot_fault_response_retry, Ut_fault_response_retry, Vin_ov_fault_response_retry, Vin_uv_fault_response_retry b[2:0] Ot_fault_response_delay, Ut_fault_response_delay, Vin_ov_fault_response_delay, Vin_uv_fault_response_delay OPERATION Response action: 2'b00: The unit continues operation without interruption. 2'b01: The device shuts down and responds according to the retry setting in bits [5:3]. 2'b10: The device shuts down and responds according to the retry setting in bits [5:3]. 2'b11: The device shuts down and responds according to the retry setting in bits [5:3]. Response action: 3'b000: A zero value for the retry setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared. 3'b001-111: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay, until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. Hard coded to 3'b000. The unit turns off immediately.
* Set the appropriate bit(s) in the STATUS_BYTE * Set the appropriate bit(s) in the STATUS_WORD * Set the appropriate bit in the corresponding STATUS_VIN or STATUS_TEMPERATURE register, and * Notify the host by pulling the ALERTB pin low.
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LTC2978 operaTion
Timed Fault Response TON_MAX_FAULT_RESPONSE This command defines the LTC2978 response to a TON_MAX_FAULT. At start-up, the TON_MAX_FAULT_ RESPONSE is disarmed once the output voltage reaches the VOUT_UNDER_VOLTAGE_LIMIT. The only way to protect against a short-circuited output at start-up is to take action in response to a TON_MAX_FAULT since VOUT_UV_FAULT_RESPONSE is not armed until the output reaches the VOUT_UNDER_VOLTAGE_LIMIT.
TON_MAX_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL b[7:6] Ton_max_fault_response_action OPERATION Response action. 2'b00: The unit continues operation without interruption. 2'b01: The unit continues operating for the delay time specified which for this type of fault corresponds to an immediate shutdown. After shutting off, the device responds according to the retry settings in bits [5:3]. 2'b1X: The device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] Ton_max_fault_response_retry Response action: 3'b000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared. 3'b001-111: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay, until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] Ton_max_fault_response_delay Hard coded to 3'b000. The unit turns off immediately.
The device also: * Sets the HIGH_BYTE bit in the STATUS_BYTE, * Sets the VOUT bit in the STATUS_WORD, * Sets the TON_MAX_FAULT bit in the STATUS_VOUT register, and * Notifies the host by asserting ALERTB.
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LTC2978 operaTion
STATUS_BYTE: The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as shown in the following table:
STATUS_BYTE Data Contents
BIT(S) SYMBOL b[7] b[6] Status_byte_busy Status_byte_off OPERATION Device busy when PMBus command received. This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. An output overvoltage fault has occurred. Not supported. Always returns 0. A VIN undervoltage fault has occurred. A temperature fault or warning has occurred. A communication, memory or logic fault has occurred. Fault/warning not listed in b[7:1].
STATUS_WORD Data Contents
BIT(S) SYMBOL b[15] Status_word_vout b[14] Status_word_iout b[13] Status_word_input b[12] Status_word_mfr OPERATION An output voltage fault or warning has occurred. Not supported. Always returns 0. An input voltage fault or warning has occurred. A manufacturer specific fault has occurred.
b[11] Status_word_power_not_good The POWER_GOOD signal, if present is negated. Power is not good. b[10] Status_word_cooling b[9] b[8] b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] Status_word_other Status_word_unknown Status_word_busy Status_word_off Status_word_vout_ov Status_word_iout_oc Status_word_vin_uv Status_word_temp Status_word_cml Status_word_high_byte Not supported. Always returns 0. Not supported. Always returns 0. Not supported. Always returns 0. Device busy when PMBus command received. Status_byte_off Status_byte_vout_ov Not supported. Always returns 0. Status_byte_vin_uv Status_byte_temp Status_byte_cml A bit in the high byte of the STATUS_WORD (b[15:8]) is set.
b[5] b[4] b[3] b[2] b[1] b[0]
Status_byte_vout_ov Status_byte_iout_oc Status_byte_vin_uv Status_byte_temp Status_byte_cml Status_byte_high_byte
STATUS_WORD: The STATUS_WORD command returns two bytes of information with a summary of the unit's fault condition. Based on the information in these bytes, the host can get more information by reading the appropriate status byte. The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command.
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STATUS_VOUT The STATUS_VOUT command returns the summary of the voltage faults or warnings which have occurred, as shown in the following table:
STATUS_VOUT Data Contents
BIT(S) SYMBOL b[7] b[6] b[5] b[4] b[3] Status_vout_ov_fault Status_vout_ov_warn Status_vout_uv_warn Status_vout_uv_fault Status_vout_max_fault OPERATION Overvoltage fault. Overvoltage warning. Undervoltage warning Undervoltage fault. VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the VOUT_MAX command. TON_MAX_FAULT sequencing fault. Not supported. Always returns 0.
STATUS_TEMPERATURE The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have occurred, as shown in the following table:
STATUS_TEMPERATURE Data Contents
Bit(s) Symbol b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] Status_temperature_ot_fault Status_temperature_ot_warn Status_temperature_ut_warn Status_temperature_ut_fault Reserved Reserved Reserved Reserved Operation Overtemperature fault. Overtemperature warning. Undertemperature warning. Undertemperature fault. Reserved. Always returns 0. Reserved. Always returns 0. Reserved. Always returns 0. Reserved. Always returns 0.
b[2] b[1] b[0]
Status_vout_ton_max_fault
Status_vout_toff_max_warn Not supported. Always returns 0. Status_vout_tracking_error
STATUS_CML The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which have occurred, as shown in the following table:
STATUS_CML Data Contents
BIT(S) SYMBOL b[7] Status_cml_cmd_fault OPERATION 1 = An illegal or unsupported command fault has occurred. 0 = No fault has occurred. b[6] Status_cml_data_fault 1 = Illegal or unsupported data received. 0 = No fault has occurred. b[5] b[4] Status_cml_pec_fault Status_cml_memory_fault 1 = A PEC fault has occurred. 0 = No fault has occurred. 1 = A fault has occurred in the NVM. 0 = No fault has occurred. b[3] b[2] b[1] Status_cml_processor_fault Not supported, always returns 0. Reserved Status_cml_PMBus_fault Not supported, always returns 0. 1 = A communication fault other than ones listed in this table has occurred. 0 = No fault has occurred. b[0] Status_cml_unknown_fault Not supported, always returns 0.
STATUS_INPUT The STATUS_INPUT command returns the summary of the VIN faults or warnings which have occurred, as shown in the following table:
STATUS_INPUT Data Contents
BIT(S) SYMBOL b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] Status_input_ov_fault Status_input_ov_warn Status_input_uv_warn Status_input_uv_fault Status_input_off IIN overcurrent fault IIN overcurrent warn PIN overpower warn OPERATION VIN Overvoltage fault VIN Overvoltage warning VIN Undervoltage warning VIN Undervoltage fault Unit is off for insufficient input voltage. Not supported. Always returns 0. Not supported. Always returns 0. Not supported. Always returns 0.
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STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC command returns manufacturer specific status flags. Bits marked FAULT = No are intended to support polled handshaking; these are not latched nor do they assert ALERTB. Bits marked Channel = All can be read from any page. Bits marked FAULT = Yes assert ALERTB low and are cleared by CLEAR_FAULTS.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL b[7] b[6] Status_mfr_discharge Status_mfr_fault1_in OPERATION 1 = A VOUT discharge fault occurred while attempting to enter the ON state 0 = No VOUT discharge fault has occurred CHANNEL Current Page FAULT Yes Yes
This channel attempted to turn on while the FAULTBz1 pin was asserted low, Current Page or this channel has shut down at least once in response to a FAULTBz1 pin asserting low since the last CONTROLn pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS command. This channel attempted to turn on while the FAULTBz0 pin was asserted low, Current Page or this channel has shut down at least once in response to a FAULTBz0 pin asserting low since the last CONTROLn pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS command. Servo target has been reached. DAC is connected and driving VDACP pin. A previous servo operation terminated with maximum or minimum DAC value. VIN_EN has been deasserted due to a VOUT fault. 1 = A watchdog fault has occurred. 0 = No watchdog fault has occurred. Current Page Current Page Current Page All All
b[5]
Status_mfr_fault0_in
Yes
b[4] b[3] b[2] b[1] b[0]
Status_mfr_servo_target_reached Status_mfr_dac_connected Status_mfr_dac_saturated Status_mfr_vinen_faulted_off Status_mfr_watchdog_fault
No No Yes No Yes
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ADC Monitoring Commands READ_VIN This command returns the most recent ADC measured value of the voltage measured at the VIN_SNS pin.
READ_VIN Data Contents
BIT(S) SYMBOL OPERATION V(Symbol) = Y * 2N where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: V b[15:0] Read_vin[15:0] The data uses the linear format:
READ_TEMPERATURE_1 This command returns the most recent ADC measured value of junction temperature in C as determined by the LTC2978's internal temperature sensor.
READ_TEMPERATURE_1 Data Contents
BIT(S) SYMBOL OPERATION Temp(Symbol) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: C. b[15:0] Read_temperature_1 [15:0] The data uses the linear format:
READ_VOUT This command returns the most recent ADC measured value of the channel's output voltage. When odd channels are configured to measure current, the data contents have a slightly modified meaning, as described in the second table below.
READ_VOUT Data Contents
BIT(S) SYMBOL OPERATION b[15:0] Read_vout[15:0] The data uses the linear mode format as defined by VOUT_MODE: V(Read_vout) = Y * 2N where Y = b[15:0] is an unsigned integer and N = Vout_mode_ parameter is a 5-bit two's complement exponent that's hardwired to -13 decimal. Units: V.
PMBUS_REVISION The PMBUS_REVISION command register is read only and reports the LTC2978 compliance to the PMBus standard revision 1.1.
PMBUS_REVISION Data Contents
BIT(S) SYMBOL b[7:0] PMBus_rev OPERATION Reports the PMBus standard revision compliance. This is hard-coded to `h11 for revision 1.1.
READ_VOUT Data Contents--for Odd Channels Configured to Measure Current
Bit(s) Symbol Operation V(Symbol) = Y * 2N where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: mV b[15:0] Read_vout[15:0] The data uses the linear format:
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MANUFACTURER SPECIFIC COMMANDS MFR_CONFIG: This command is used to configure various manufacturer specific operating parameters for each channel.
MFR_CONFIG Data Contents
BIT(S) SYMBOL b[15:12] Reserved b[11] Mfr_config_fast_servo_off OPERATION Don't care. Always returns 0. Disables fast servo when margining or trimming output voltages: 0: fast-servo enabled. 1: fast-servo disabled. Mfr_config_supervisor_resolution Selects supervisor resolution: 0: high resolution - 4mV/LSB, range for VSENSEP is 0V to 3.8V. 1: low resolution - 8mV/LSB, range for VSENSEP is 0V to 6.0V. Mfr_config_adc_hires Selects ADC resolution for odd channels. Ignored for even channels (they always use low res). 0: low resolution - 122V/LSB. 1: high resolution - 15.6V/LSB. Mfr_config_controln_sel Selects the active control pin input (CONTROL0 or CONTROL1) for this channel. 0: Select CONTROL0 pin. 1: Select CONTROL1 pin. Mfr_config_servo_continuous Select whether the UNIT should continuously servo VOUT after it has reached a new margin or nominal target. Only applies when Mfr_dac_mode = 2'b00. 0: Do not continuously servo VOUT after reaching initial target. 1: Continuously servo VOUT to target. Mfr_config_servo_on_warn Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = 2'b00 and Mfr_config_servo_continuous = 0. 0: Do not allow the unit to re-servo when a VOUT warning threshold is met or exceeded. 1: Allow the unit to re-servo VOUT to nominal target if VOUT V(Vout_ov_warn_limit) or VOUT V(Vout_uv_warn_limit). Mfr_config_dac_mode Determines how DAC is used when channel enters ON state or is already in ON state. 00: Soft connect (if needed) and servo to target. Wait for TON_RISE if just entering ON state. 01: DAC not connected. 10: DAC connected using value from MFR_DAC command. Does not wait for TON_RISE if just entering ON state. 11: DAC is soft connected. After soft connect is complete MFR_DAC may be written. Mfr_config_vo_en_wpu_en VO_EN charge pumped, current-limited pull-up enable. 0: Disable weak pull-up. VO_EN driver is three-stated when channel is on. 1: Use weak current-limited pull-up on VO_EN when the channel is on. For channels 4-7 this bit is treated as a 0 regardless of its value. Mfr_config_vo_en_wpd_en VO_EN current-limited pull-down enable. 0: Use a fast N-channel device to pull down VO_EN when the channel is off for any reason. 1: Use weak current-limited pull-down to discharge VO_EN when channel is off due to soft stop by the CONTROLn pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down on VO_EN. For channels 4-7 this bit is treated as a 0 regardless of its value. Mfr_config_dac_gain DAC buffer gain. 0: Select DAC buffer gain dac_gain_0 (1.38V full-scale) 1: Select DAC buffer gain dac_gain_1 (2.65V full-scale) Mfr_config_dac_pol DAC output polarity. 0: Encodes negative (inverting) DC/DC converter trim input. 1: Encodes positive (noninverting) DC/DC converter trim input.
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b[10]
b[9]
b[8]
b[7]
b[6]
b[5:4]
b[3]
b[2]
b[1]
b[0]
LTC2978 operaTion
MFR_CONFIG_ALL: This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed from any PAGE setting.
MFR_CONFIG_ALL Data Contents
BIT(S) SYMBOL b[7] Mfr_config_fault_log_enable OPERATION Enable fault logging to NVM in response to Fault. 0: Fault logging to NVM is disabled 1: Fault logging to NVM is enabled VIN_ON rising edge to clear all latched faults 0: VIN_ON clear faults feature is disabled 1: VIN_ON clear faults feature is enabled Selects active polarity of control1 pin. 0: Active low (pull pin low to start unit) 1: Active high (pull pin high to start unit) Selects active polarity of control0 pin. 0: Active low (pull pin low to start unit) 1: Active high (pull pin high to start unit)
MFR_CONFIG_ALL Data Contents
b[3] Mfr_config_vin_share_enable Allow this unit to hold shareclock pin low when VIN_ON has fallen below VIN_OFF When . enabled, this unit will also turn all channels off in response to share-clock being held low. 0: Share-clock inhibit is disabled 1: Share-clock inhibit is enabled Mfr_config_all_pec_en PMBus packet error checking enable. 0: PEC is accepted but not required 1: PEC is required Mfr_config_all_longer_ Increase PMBus timeout internal pmbus_timeout by a factor of 8. 0: PMBus timeout is not multiplied by a factor of 8 1: PMBus timeout is multiplied by a factor of 8 Mfr_config_all_vinen_wpu_ VIN_EN charge pumped, currentdis limited pull-up disable. 0: Use weak current-limited pullup on VIN_EN after power-up, as long as no faults have forced VIN_EN off. 1: Disable weak pull-up. VIN_EN driver is three-stated after power-up as long as no faults have forced VIN_EN off.
b[6]
Mfr_vin_on_clr_faults_en
b[2]
b[5]
Mfr_config_control1_pol
b[1]
b[4]
Mfr_config_control0_pol
b[0]
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MFR_FAULTB00_PROPAGATE, MFR_FAULTB01_ PROPAGATE, MFR_FAULTB10_PROPAGATE and MFR_FAULTB11_PROPAGATE These manufacturer specific commands enable channels that have faulted off to propagate that state to the appropriate fault pin. There are two zones in the LTC2978. In zone 0, faulted off states for channels 0 through 3 can be propagated to FAULT00 or FAULT01. In zone 1, faulted off states for channels 4 through 7 can be propagated to FAULT10 or FAULT11. See Figure 13.
MFR_FAULTB00_PROPAGATE Data Contents--Fault Zone 0 (Pages 0-3)
BIT(S) SYMBOL b[7:1] Reserved b[0] Mfr_faultb00_propagate OPERATION Don't care. Always returns 0. Enable fault propagation. 0: FAULTB00 will not be affected if a fault is declared. 1: FAULTB00 will be asserted low if a fault is declared.
MFR_FAULTB10_PROPAGATE Data Contents--Fault Zone 1 (Pages 4-7)
BIT(S) SYMBOL b[7:1] Reserved b[0] Mfr_faultb10_propagate OPERATION Don't care. Always returns 0. Enable fault propagation. 0: FAULTB10 will not be affected if a fault is declared. 1: FAULTB10 will be asserted low if a fault is declared.
MFR_FAULTB11_PROPAGATE Data Contents--Fault Zone 1 (Pages 4-7)
BIT(S) SYMBOL b[7:1] Reserved b[0] Mfr_faultb11_propagate OPERATION Don't care. Always returns 0. Enable fault propagation. 0: FAULTB11 will not be affected if a fault is declared. 1: FAULTB11 will be asserted low if a fault is declared.
MFR_FAULTB01_PROPAGATE Data Contents--Fault Zone 0 (Pages 0-3)
BIT(S) SYMBOL b[7:1] Reserved b[0] Mfr_faultb01_propagate OPERATION Don't care. Always returns 0. Enable fault propagation. 0: FAULTB01 will not be affected if a fault is declared. 1: FAULTB01 will be asserted low if a fault is declared.
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MFR_PWRGD_EN This command register controls the mapping of power good status to the power good pin. Note that odd numbered channels whose ADC is in high res mode do not contribute to power good.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL b[15:9] Reserved b[8] Mfr_pwrgd_en_wdog OPERATION Read only, always returns 0s. Watchdog 1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = Watchdog timer does not affect the PWRGD pin. b[7] Mfr_pwrgd_en_chan7 Channel 7 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[6] Mfr_pwrgd_en_chan6 Channel 6 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[5] Mfr_pwrgd_en_chan5 Channel 5 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[4] Mfr_pwrgd_en_chan4 Channel 4 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[3] Mfr_pwrgd_en_chan3 Channel 3 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[2] Mfr_pwrgd_en_chan2 Channel 2 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[1] Mfr_pwrgd_en_chan1 Channel 1 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[0] Mfr_pwrgd_en_chan0 Channel 0 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin.
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MFR_FAULTB00_RESPONSE, MFR_FAULTB01_ RESPONSE, MFR_FAULTB10_RESPONSE and MFR_ FAULTB11_RESPONSE These manufacturer specific commands share the same format and specify the response to assertions of the bidirectional fault pins. For fault zone 0, MFR_FAULTB00_RESPONSE determines how channels 0-3 respond when the FAULTB00 pin is asserted, and MFR_FAULTB01_ RESPONSE determines how channels 0-3 respond
Data Contents--Fault Zone 0 Response Commands
BIT(S) SYMBOL b[7:4] Reserved b[3] Mfr_faultb00_response_chan3, Mfr_faultb01_response_chan3 OPERATION Read only, always returns 0s. Channel 3 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 2 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 1 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 0 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
when the FAULTB01 pin is asserted. For fault zone 1, MFR_FAULTB10_RESPONSE determines how channels 4-7 respond when the FAULTB10 pin is asserted, and MFR_FAULTB11_RESPONSE determines how channels 4-7 respond when the FAULTB11 pin is asserted. If one or more bits in the MFR_FAULTBzn_RESPONSE registers are set, a FAULTBzn assertion will cause the ALERTB pin to assert low and set the appropriate bit in the STATUS_MFR_ SPECIFIC register.
b[2]
Mfr_faultb00_response_chan2, Mfr_faultb01_response_chan2
b[1]
Mfr_faultb00_response_chan1, Mfr_faultb01_response_chan1
b[0]
Mfr_faultb00_response_chan0, Mfr_faultb01_response_chan0
Data Contents--Fault Zone 1 Response Commands
BIT(S) SYMBOL b[7:4] Reserved b[3] Mfr_faultb10_response_chan7, Mfr_faultb11_response_chan7 OPERATION Read only, always returns 0s. Channel 7 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 6 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 5 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 4 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10s. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
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b[2]
Mfr_faultb10_response_chan6, Mfr_faultb11_response_chan6
b[1]
Mfr_faultb10_response_chan5, Mfr_faultb11_response_chan5
b[0]
Mfr_faultb10_response_chan4, Mfr_faultb11_response_chan4
LTC2978 operaTion
MFR_VINEN_OV_FAULT_RESPONSE This command register determines whether VOUT over voltage faults from a given channel cause the VIN_EN pin to be forced off.
MFR_VINEN_OV_FAULT_RESPONSE Data Contents
BIT(S) b[7] SYMBOL Mfr_vinen_ov_fault_response_chan7 OPERATION Response to channel 7 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[6] Mfr_vinen_ov_fault_response_chan6 Response to channel 6 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[5] Mfr_vinen_ov_fault_response_chan5 Response to channel 5 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[4] Mfr_vinen_ov_fault_response_chan4 Response to channel 4 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[3] Mfr_vinen_ov_fault_response_chan3 Response to channel 3 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[2] Mfr_vinen_ov_fault_response_chan2 Response to channel 2 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[1] Mfr_vinen_ov_fault_response_chan1 Response to channel 1 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[0] Mfr_vinen_ov_fault_response_chan0 Response to channel 0 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is.
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LTC2978 operaTion
MFR_VINEN_UV_FAULT_RESPONSE This command register determines whether VOUT under voltage faults from a given channel cause the VIN_EN pin to be forced off.
MFR_VINEN_UV_FAULT_RESPONSE Data Contents
BIT(S) b[7] SYMBOL Mfr_vinen_uv_fault_response_chan7 OPERATION Response to channel 7 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[6] Mfr_vinen_uv_fault_response_chan6 Response to channel 6 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[5] Mfr_vinen_uv_fault_response_chan5 Response to channel 5 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[4] Mfr_vinen_uv_fault_response_chan4 Response to channel 4 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[3] Mfr_vinen_uv_fault_response_chan3 Response to channel 3 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[2] Mfr_vinen_uv_fault_response_chan2 Response to channel 2 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[1] Mfr_vinen_uv_fault_response_chan1 Response to channel 1 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[0] Mfr_vinen_uv_fault_response_chan0 Response to channel 0 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is.
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MFR_RETRY_DELAY This command determines the retry interval when the LTC2978 is in hiccup mode in response to a fault condition.
MFR_RETRY_DELAY Data Contents
BIT(S) SYMBOL OPERATION T(Symbol) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer This delay is counted using SHARE_CLK only. Delays are rounded to the nearest 200s. Units: ms. Max delay is 13.1 sec. b[15:0] Mfr_retry_delay The data uses the linear format:
MFR_VOUT_PEAK This command returns the maximum ADC measured value of the channel's output voltage. This command is not supported for odd channels that are configured to measure current. This register is reset to zero when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_PEAK Data Contents
BIT(S) SYMBOL OPERATION b[15:0] Mfr_vout_peak[15:0] The data uses the linear mode format as defined by VOUT_MODE: V(mfr_vout_peak) = Y * 2N where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two's complement exponent that's hardwired to -13 decimal. Units: V.
MFR_RESTART_DELAY This command determines how the CONTROLn pins are adjusted before use. The time the adjusted version of the CONTROLn pin is in the off polarity is stretched by this command to be at least Mfr_restart_delay ms. CONTROLn pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value of all zeros disables this feature.
MFR_RESTART_DELAY Data Contents
BIT(S) SYMBOL OPERATION T(Symbol) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer This delay is counted using SHARE_CLK only. Delays are rounded to the nearest 200s. Units: ms. Max delay is 13.1 sec. b[15:0] Mfr_restart_delay The data uses the linear format:
MFR_VIN_PEAK This command returns the maximum ADC measured value of the input voltage. The contents of this register are reset to `h7C00 when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VIN_PEAK Data Contents
BIT(S) SYMBOL OPERATION V(Symbol) = Y * 2N where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: V b[15:0] Mfr_vin_peak[15:0] The data uses the linear format:
MFR_TEMPERATURE_PEAK This command returns the maximum ADC measured value of junction temperature in C as determined by the LTC2978's internal temperature sensor. The contents
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of this register are reset to `h7C00 when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_PEAK Data Contents
BIT(S) SYMBOL OPERATION V(Symbol) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: C. b[15:0] Mfr_temperature_peak[15:0] The data uses the linear format:
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval following assertion of the POWER GOOD signal, assuming the POWER GOOD signal reflects the status of the watchdog timer. If assertion of POWER GOOD is not conditioned by the watchdog timer's status, then MFR_WATCHDOG_T_FIRST applies to the first timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables the watchdog timer. The MFR_WATCHDOG_T register allows the user to program watchdog time intervals subsequent to the MFR_WATCHDOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog timer. A non-zero write to MFR_WATCHDOG_T will reset the watchdog timer.
MFR_WATCHDOG_T_POR and MFR_WATCHDOG_T Data Contents
BIT(S) SYMBOL OPERATION b[15:0] Mfr_watchdog_t_first The data uses the linear format: Mfr_watchdog_t T(Symbol) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer These timers operate on an internal clock independent of SHARE_CLK. Delays are rounded to the nearest 10s for _t and 1ms for _t_first. Writing a zero value for Y to the Mfr_watchdog_t or Mfr_watchdog_t_ first registers will disable the watchdog timer. Units: ms. Max timeout is 0.6 sec for _t and 65 sec for _t_first
MFR_DAC This command register returns the 10-bit value for the voltage-buffered current DAC. This register may be written when Mfr_config_dac_mode is configured for either of the two manual DAC modes.
MFR_DAC Data Contents
BIT(S) b[9:0] SYMBOL OPERATION Read only, always returns `h3F . b[15:10] Reserved
Mfr_dac_direct_val Voltage-buffered current DAC code value.
MFR_POWERGOOD_ASSERTION_DELAY This command register allows the user to program the delay from when the internal power good signal becomes valid until the power good output is asserted.
MFR_POWERGOOD_ASSERTION_DELAY Data Contents
BIT(S) SYMBOL OPERATION T(Symbol) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer. This delay is counted using internal clock independent of SHARE_CLK. Delays are rounded to the nearest 200s Units: ms. Max delay is 13.1 sec. b[15:0] Mfr_powergood_assertion_delay The data uses the linear format:
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MFR_PAGE_FF_MASK The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page (FF) is in use. Note that the only commands that support PAGE = `hFF are OPERATION and ON_OFF_CONFIG.
MFR_PAGE_FF_MASK Data Contents
BIT(S) SYMBOL OPERATION b[7:0] Mfr_page_ff_mask Global page response enable, per channel Each bit enables/disables the corresponding channel: 0 = ignore global page accesses 1 = fully respond to global page accesses b[3:0] Mfr_pads_faultb[3:0] b[5] Mfr_pads_control1 1: Logic high detected on CONTROL1 pad 0: Logic low detected on CONTROL1 pad 1: Logic high detected on CONTROL0 pad 0: Logic low detected on CONTROL0 pad Bit[3] used for FAULTB00 pad, bit[2] used for FAULTB01 pad, bit[1] used for FAULTB10 pad, bit[0] used for FAULTB11 pad as follows: 1: Logic high detected on FAULTBzn pad 0: Logic low detected on FAULTBzn pad
b[4]
Mfr_pads_control0
MFR_PADS The MFR_PADS command provides read only access to slow frequency digital pads. The input values presented in bits[9:0] are before any deglitching logic.
MFR_PADS_PWRGD_DRIVE Data Contents
BIT(S) SYMBOL b[15] Mfr_pads_pwrgd_drive OPERATION 0 = PWRGD pad is being driven low by this chip 1 = PWRGD pad is not being driven low by this chip 0 = ALERTB pad is being driven low by this chip
MFR_I2C_BASE_ADDRESS The MFR_I2C_BASE_ADDRESS command determines the base value for the I2C address byte.
MFR_I2C_BASE_ADDRESS Data Contents
BIT(S) SYMBOL b[7] Reserved b[6:0] i2c_base_address OPERATION Read only, always returns 0. This 7-bit value determines the base value of the 7-bit I2C address.
b[14]
Mfr_pads_alertb_drive
1 = ALERTB pad is not being driven low by this chip b[13:10] Mfr_pads_faultb_drive[3.0] Bit[3] used for FAULTB00 pad, bit[2] used for FAULTB01 pad, bit[1] used for FAULTB10 pad, bit[0] used for FAULTB11 pad as follows: 0 = FAULTB pad is being driven low by this chip 1 = FAULTB pad is not being driven low by this chip 11: Logic high detected on ASEL1 input pad 10: ASEL1 input pad is floating 01: Reserved 00: Logic low detected on ASEL1 input pad 11: Logic high detected on ASEL0 input pad 10: ASEL0 input pad is floating 01: Reserved 00: Logic low detected on ASEL0 input pad
MFR_SPECIAL_ID This register contains the manufacturer ID for the LTC2978.
MFR_SPECIAL_ID Data Contents
BIT(S) b[15:0] SYMBOL Mfr_special_id OPERATION Read only, always returns `h0121
MFR_SPECIAL_LOT These paged registers contain information that identifies the user configuration that was programmed at the factory.
MFR_SPECIAL_LOT Data Contents
BIT(S) b[7:0] SYMBOL Mfr_special_lot OPERATION Contains the LTC default special lot number. Contact the factory to request a custom factory programmed user configuration and special lot number.
b[9:8]
Mfr_pads_asel1[1:0]
b[7:6]
Mfr_pads_asel0[1:0]
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MFR_VOUT_DISCHARGE_THRESHOLD This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF threshold voltage for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_ THRESHOLD * VOUT_COMMAND prior to the channel being commanded to enter/re-enter the ON state, bit [7] in the STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In addition, the channel will not enter the ON state until the output has decayed below its OFF threshold voltage. Other channels can be held off if a particular output has failed to discharge by using the bidirectional FAULTzn pins (refer to the MFR_FAULTBzn_RESPONSE and MFR_FAULTBzn_PROPAGATE registers).
MFR_VOUT_DISCHARGE_THRESHOLD Data Contents
BIT(S) b[15:0] SYMBOL Mfr_vout_discharge_ threshold OPERATION The data uses the linear format: k = Y * 2N Where N=b[15:11] is a 5-bit two's complement integer and Y= b[10:0] is an 11-bit two's complement integer. Units: Dimensionless, this register contains a coefficient.
MFR_FAULT_LOG_CLEAR This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will be erased by this operation. MFR_FAULT_LOG_STATUS Read only. This register is used to manage fault log events. Mfr_fault_log_status_eeprom is set after a MFR_FAULT_ LOG_STORE command or a faulted-off event triggers a transfer of the fault log from RAM to EEPROM. This bit is cleared by a MFR_FAULT_LOG_CLEAR command. Mfr_fault_log_status_ram is set after a MFR_FAULT_ LOG_RESTORE to indicate that the data in the RAM has been restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared by a MFR_FAULT_LOG command.
MFR_FAULT_LOG_STATUS Data Contents
BIT(S) SYMBOL b[1] Mfr_fault_log_status_ram OPERATION Fault log RAM status: 0: The fault log RAM allows updates. 1: The fault log RAM is locked until the next Mfr_fault_log read. b[0] Mfr_fault_log_status_eeprom Fault log EEPROM status: 0: The transfer of the fault log RAM to the EEPROM is enabled. 1: The transfer of the fault log RAM to the EEPROM is inhibited.
MFR_FAULT_LOG_STORE This command allows the user to transfer data from the RAM buffer to EEPROM. MFR_FAULT_LOG_RESTORE This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a restore the RAM buffer is locked until a successful Mfr_fault_log read.
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MFR_FAULT_LOG Read only. This 2048-bit data block contains a copy of the RAM buffer fault log. The RAM buffer is continuously updated after each ADC conversion as long as Mfr_fault_ log_status_ram is clear. With Mfr_config_fault_log_en = 1 and Mfr_fault_log_status_eeprom = 0, the RAM buffer is transferred to EEPROM whenever an LTC2978 fault causes a channel to latch off or a MFR_FAULT_LOG_STORE command is received. Mfr_fault_log_status_eeprom is set high after the RAM buffer is transferred to EEPROM and not cleared until a Mfr_fault_log_clear is received; even if the LTC2978 is reset or powered down. Fault log EEPROM transfers are not initiated as a result of Status_mfr_discharge, Status_mfr_fault1_in or Status_mfr_fault0_in events. During a Mfr_fault_log read, data is returned one byte at a time as defined by the following table. The fault log stores approximately 1 to 2 seconds of telemetry.
MFR_FAULT_LOG Data Block Contents DATA BYTE Position_last[7:0] 0 SharedTime[7:0] SharedTime[15:8] SharedTime[23:16] SharedTime[31:24] SharedTime[39:32] SharedTime[40] Mfr_vout_peak0[7:0] Mfr_vout_peak0[15:8] Mfr_vout_min0[7:0] Mfr_vout_min0[15:8] Mfr_vout_peak1[7:0] Mfr_vout_peak1[15:8] Mfr_vout_min1[7:0] Mfr_vout_min1[15:8] Mfr_vin_peak[7:0] Mfr_vin_peak[15:8] Mfr_vin_min[7:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 BLOCK READ COMMAND Position of fault log pointer when fault occurred. 41-bit share-clock counter value when fault occurred. Counter LSB is in 200s increments. This counter is cleared at power-up or after the LTC2978 is reset MFR_FAULT_LOG Data Block Contents DATA BYTE Mfr_vin_min[15:8] 18 Mfr_vout_peak2[7:0] 19 Mfr_vout_peak2[15:8] 20 Mfr_vout_min2[7:0] 21 Mfr_vout_min2[15:8] 22 Mfr_vout_peak3[7:0] 23 Mfr_vout_peak3[15:8] 24 Mfr_vout_min3[7:0] 25 Mfr_vout_min3[15:8] 26 Mfr_temp_peak[7:0] 27 Mfr_temp_peak[15:8] 28 Mfr_ temp_min[7:0] 29 Mfr_ temp_min[15:8] 30 Mfr_vout_peak4[7:0] 31 Mfr_vout_peak4[15:8] 32 Mfr_vout_min4[7:0] 33 Mfr_vout_min4[15:8] 34 Mfr_vout_peak5[7:0] 35 Mfr_vout_peak5[15:8] 36 Mfr_vout_min5[7:0] 37 Mfr_vout_min5[15:8] 38 Mfr_vout_peak6[7:0] 39 Mfr_vout_peak6[15:8] 40 Mfr_vout_min6[7:0] 41 Mfr_vout_min6[15:8] 42 Mfr_vout_peak7[7:0] 43 Mfr_vout_peak7[15:8] 44 Mfr_vout_min7[7:0] 45 Mfr_vout_min7[15:8] 46 Fault_log [Position_last] Fault_log [Position_last-1] . . . Fault_log [Position_last-201] Reserved 47 48 BLOCK READ COMMAND
47 bytes for preamble
247 248-255 Number of loops (248-47)/40 = 5
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Data is logged into memory in the order shown in the following table. When data is returned during a block read it is returned in reverse order based on the value of Position_last[7:0]. Data byte Read_vout0[7:0] is followed by Status_mfr of page 7. Example: If Position_last = 9 then the first data returned in byte position 47 of a block read is Read_vin[15:8] followed by Read_vin[7:0] followed by Status_mfr of page 1.
POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DATA Read_vout0[7:0] Read_vout0[15:8] Status_vout0 Status_mfr0 Read_vout1[7:0] Read_vout1[15:8] Status_vout1 Status_mfr1 Read_vin[7:0] Read_vin[15:8] Status_vin Reserved Read_vout2[7:0] Read_vout2[15:8] Status_vout2 Status_mfr2 Read_vout3[7:0] Read_vout3[15:8] Status_vout3 Status_mfr3 Read_temperature_1[7:0] Read_temperature_1[15:8] Status_temp Reserved Read_vout4[7:0] Read_vout4[15:8] Status_vout4 Status_mfr4 Read_vout5[7:0] Read_vout5[15:8] Status_vout5 Status_mfr5 POSITION 32 33 34 35 36 37 38 39 DATA Read_vout6[7:0] Read_vout6[15:8] Status_vout6 Status_mfr6 Read_vout7[7:0] Read_vout7[15:8] Status_vout7 Status_mfr7 Total Bytes =40
MFR_COMMON This command returns status information for the shareclock pin (SCLK) and the write-protect pin (WP).
MFR_COMMON Data Contents
BIT(S) b[7:2] b[1] SYMBOL Reserved Mfr_common_ share_clk Mfr_common_ write_protect OPERATION Read only, always returns 0s Returns status of share-clock pin 1: Share-clock pin is being held low 0: Share-clock pin is active b[0] Returns status of write-protect pin 1: Write-protect pin is high 0: Write-protect pin is low
MFR_SPARE0 This 16-bit wide registers can be used to store miscellaneous information. The contents of these registers may be stored and recalled from EEPROM using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. MFR_SPARE2 These 16-bit wide, paged registers can be used to store miscellaneous information. The contents of these registers may be stored and recalled from EEPROM using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively.
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MFR_VOUT_MIN This command returns the minimum ADC measured value of the channel's output voltage. The contents of this register is reset to `hFFFF when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. When odd channels are configured to measure current, this command is not supported.
MFR_VOUT_MIN Data Contents
BIT(S) b[15:0] SYMBOL Mfr_vout_min OPERATION The data uses the linear mode format as defined by VOUT_MODE: V(mfr_vout_min) = Y * 2N Where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two's complement exponent that's hardwired to a value of -13 decimal. Units: V.
MFR_TEMPERATURE_MIN This command returns the minimum ADC measured value of junction temperature in C as determined by the LTC2978's internal temperature sensor. The contents of this register is reset to `h7BFF when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_MIN Data Contents
BIT(S) SYMBOL OPERATION V(mfr_vin_min) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: C. b[15:0] Mfr_temperature_min The data uses the linear format:
MFR_VIN_MIN This command returns the minimum ADC measured value of the input voltage. The contents of this register is reset to `h7BFF when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. Updates are disabled when unit is off for insufficient input voltage.
MFR_VIN_MIN Data Contents
BIT(S) b[15:0] SYMBOL Mfr_vin_min OPERATION The data uses the linear format: V(mfr_vin_min) = Y * 2N Where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer Units: V.
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WATCHDOG A non-zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the WDI pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output is optionally deasserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the MFR_WATCHDOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer. RESET Holding the WDI pin low for more than tRESETB will cause the LTC2978 to enter the power-on reset state. Following the subsequent rising-edge of the WDI pin, the LTC2978 will execute its power-on sequence per the user configuration stored in EEPROM. WRITE-PROTECT PIN The WP pin allows the user to write-protect the LTC2978's configuration registers. The WP pin is active high, and when asserted it overrides the WRITE_PROTECT command register. All registers are write-protected by the WP pin except for PAGE, OPERATION, CLEAR_FAULTS, MFR_PAGE_FF_MASK and STORE_USER_ALL. OTHER OPERATIONS Clock Sharing Multiple LTC2978s can synchronize their clocks in an application by connecting together the open-drain SHARE_CLK input/outputs to a pull-up resistor as a wired AND. In this case the fastest clock will take over and synchronize all LTC2978s. The LTC2978 can be configured to respond to the SHARE_CLK pin being held low by disabling all channels after a brief de-glitch period. When the SHARE_CLK pin is allowed to rise, the LTC2978 will respond by beginning a soft-start sequence. The LTC2978 can be configured to hold SHARE_CLK low when the unit is off for insufficient input voltage by writing b[3] = 1 "mfr_config_vin_share_enable" of the MFR_CONFIG_ALL register.
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LTC2978 Overview The LTC2978 is a power management IC that is capable of sequencing, margining, trimming, OV/UV supervision, providing fault management, and voltage read back for eight DC/DC converters. Input voltage and temperature read back is also available. Odd numbered channels can be configured to read back sense resistor voltages. Multiple LTC2978s can be synchronized to operate in unison using the SHARE_CLK, FAULTB and CONTROL pins. The LTC2978 utilizes a PMBus compliant interface and command set. Setting Command Register Values The command register settings described herein are for the purpose of understanding and software development in a host processor. In actual practice, the LTC2978 can be completely configured for standalone operation with the LTC DC590B dongle and software GUI using intuitive menu driven objects. Command Units On or Off Three control parameters determine how a particular channel is turned on and off. The CONTROLn pins, the OPERATION command and the value of the input voltage measured at the VIN_SNS pin (VIN). In all cases, VIN must exceed VIN_ON in order to enable a start. When VIN drops below VIN_OFF , an immediate shutdown of all channels will result. Refer to the OPERATION section in the data sheet for a detailed description of the ON_OFF_CONFIG command.
VCONTROL VOUT_EN
Some examples of typical ON/OFF configurations are: 1. A DC/DC may be configured to turn on anytime VIN exceeds VIN_ON. 2. A DC/DC may be configured to turn on only when it receives an OPERATION command. 3. A DC/DC may be configured to turn on only via the CONTROL pin. 4. A DC/DC may be configured to turn on only when it receives an OPERATION command and the CONTROL pin is asserted. On Sequencing The TON_DELAY command sets the amount of time that a channel will wait following the start of an ON sequence before its VOUT_ENn pin will enable a DC/DC converter. Once the DC/DC converter has been enabled, the TON_RISE command determines the amount of time the LTC2978 waits before the VDACPnoutput is soft-connected and the DC/DC converter output is servoed to VOUT_COMMAND volts. The TON_MAX_FAULT_LIMIT command determines the amount of time after the DC/DC converter has been enabled that an undervoltage condition will be tolerated before a fault occurs. If a TON_MAX_FAULT occurs, the channel can be configured to disable the DC/DC converter and propagate the fault to other channels using the bidirectional FAULTBzn pins. Figure 11 shows a typical onsequence using the CONTROL pin.
VOUT_0V_FAULT_LIMIT DAC SOFT-CONNECTS AND BEGINS ADJUSTING OUTPUT VOUT VOUT_COMMAND VDC_NOM VOUT_UV_FAULT_LIMIT
2978 F11
TON_DELAY
TON_RISE TON_MAX_FAULT_LIMIT
Figure 11. Typical On Sequence Using Control Pin
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ON State Operation Once a channel has reached the ON state, the OPERATION command can be used to command the DC/DC converter's output to margin high, margin low, or return to a nominal output voltage indicated by VOUT_COMMAND. The user also has the option of configuring a channel to continuously trim the output of the DC/DC converter to the VOUT_COMMAND voltage, or the channel's VDACPnoutput can be placed in a high impedance state thus allowing the DC/DC converter output voltage to go to its nominal value, VDCn(NOM). Refer to the MFR_CONFIG command for details on how to configure the output voltage servo. Off Sequencing An off sequence is initiated using the CONTROLn pin or the OPERATION command. The TOFF_DELAY command determines the amount of time that elapses from the beginning of the off sequence until each channel's VOUT_EN pin is pulled low thus disabling its DC/DC converter. VOUT Off Threshold Voltage The MFR_VOUT_DISCHARGE_THRESHOLD command register allows the user to specify the OFF threshold that the output voltage must decay below before the channel can enter/re-enter the ON state. The OFF threshold voltage is specified by multiplying MFR_VOUT_DISCHARGE_THRESHOLD and VOUT_COMMAND. In the event that an output voltage has not decayed below its OFF threshold before attempting to enter the ON state, the channel will continue to be held off, the appropriate bit is set in the STATUS_MFR_SPECIFIC register, and the
CONTROL PIN BOUNCE VCONTROL
ALERTB pin will be asserted low. When the output voltage has decayed below its OFF threshold, the channel can enter the ON state. Automatic Restart via MFR_RESTART_DELAY Command If the CONTROLn pin is toggled quickly (>10s deglitch), an automatic restart sequence can be triggered using the MFR_RESTART_DELAY command for the channels enabled by the CONTROLn pin (see Figure 12). VOUT OV/UV Faults The high speed voltage supervisor OV and UV fault thresholds are configured using the VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT commands, respectively. The VOUT_UV_FAULT_RESPONSE and VOUT_UV_FAULT_ RESPONSE commands determine the response to an OV/UV fault. Fault responses can range from disabling the DC/DC converter immediately, waiting to see if the fault condition persists for some interval before disabling the DC/DC converter, or allowing the DC/DC converter to continue operating in spite of the fault. If a DC/DC converter is disabled, the LTC2978 can be configured to retry or latch-off. The retry interval is specified using the MFR_RETRY_DELAY command. Latched faults are reset by toggling the CONTROLn pin, using the OPERATION command, or removing and reapplying the bias voltage (VIN_SNS pin). All fault and warning conditions result in the ALERTB pin being asserted low and the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the status registers and deasserts the ALERTB output.
VOUT_END
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TOFF_DELAY0
MFR_RESTART_DELAY
TON_DELAY0
Figure 12. Off Sequence with Automatic Restart
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VOUT OV/UV Warnings OV and UV warning threshold voltages are processed by the LTC2978's ADC. These thresholds are set by the VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT commands. If a warning occurs, the corresponding bits are set in the status registers and the ALERTB output is asserted low. Note that a warning will never cause a VOUT_ENn output to disable a DC/DC converter. Configuring the VIN_EN Output The VIN_EN output may be used to disable the intermediate bus voltage in the event of an output OV or UV fault. Use the MFR_VINEN_OV_FAULT_RESPONSE and MFR_VINEN_UV_FAULT_RESPONSE registers to configure the VIN_EN pin to assert low in response to VOUT_OV/UV fault conditions. The VIN_EN output will stop pulling low when the LTC2978 is commanded to re-enter the ON state following a faulted-off condition. A charge-pumped 5A pull-up to 12V is also available on the VIN_EN output. Refer to the MFR_CONFIG_ALL register description in the OPERATION section for more information. Figure 23 shows an application circuit where the VIN_EN output is used to trigger a SCR crowbar on the intermediate bus in order to protect the DC/DC converter's load from a catastrophic fault such as a stuck top gate. Multichannel Fault Management Multichannel fault management is handled using the bidirectional FAULTBzn pins. The "z" designates the fault zone which is either 0 or 1. There are two fault zones in the LTC2978. Each zone contains 4-channels. Figure 13 illustrates the connections between channels and the FAULTBzn pins. * The MFR_FAULTBz0_PROPAGATE command acts like a programmable switch that allows faulted-off conditions from a particular channel (PAGE) to propagate to either FAULTBzn output in that channel's zone. The MFR_FAULTBzn_RESPONSE command controls similar switches on the inputs to each channel that allow any channel to shut down in response to any combination of the FAULTBzn pins within a zone. Channels responding to a FAULTBzn pin pulling low will attempt a new start sequence when the FAULTBzn pin in question is released by the faulted channel. * To establish dependencies across fault zones, tie the fault pins together, e.g., FAULTB01 to FAULTB10. Any channel can depend on any other. To disable all channels in response to any channel faulting off, short all the FAULTBzn pins together, and set MFR_FAULTBzn_ PROPAGATE = `h01 and MFR_FAULTBzn_RESPONSE = `h0F for all channels. * A FAULTBzn pin can also be asserted low by an external driver in order to initiate an immediate off-sequence after a 10s deglitch delay.
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MFR_FAULTB00_RESPONSE, PAGE = 0 MFR_FAULTB01_RESPONSE, PAGE = 0 MFR_FAULTB00_RESPONSE, PAGE = 1 MFR_FAULTB01_RESPONSE, PAGE = 1 MFR_FAULTB00_RESPONSE, PAGE = 2 MFR_FAULTB01_RESPONSE, PAGE = 2 MFR_FAULTB00_RESPONSE, PAGE = 3 MFR_FAULTB01_RESPONSE, PAGE = 3 ZONE 0 ZONE 1 CHANNEL 3 EVENT PROCESSOR PAGE = 3 CHANNEL 2 EVENT PROCESSOR PAGE = 2 CHANNEL 1 EVENT PROCESSOR PAGE = 1 CHANNEL 0 EVENT PROCESSOR PAGE = 0
MFR_FAULTB00_PROPAGATE, PAGE = 0 MFR_FAULTB01_PROPAGATE, PAGE = 0 MFR_FAULTB00_PROPAGATE, PAGE = 1 MFR_FAULTB01_PROPAGATE, PAGE = 1 MFR_FAULTB00_PROPAGATE, PAGE = 2 MFR_FAULTB01_PROPAGATE, PAGE = 2 MFR_FAULTB00_PROPAGATE, PAGE = 3 MFR_FAULTB01_PROPAGATE, PAGE = 3 ZONE 0 ZONE 1 FAULTB00
FAULTB01
MFR_FAULTB10_RESPONSE, PAGE = 4 MFR_FAULTB11_RESPONSE, PAGE = 4 MFR_FAULTB10_RESPONSE, PAGE = 5 MFR_FAULTB11_RESPONSE, PAGE = 5 MFR_FAULTB10_RESPONSE, PAGE = 6 MFR_FAULTB11_RESPONSE, PAGE = 6 MFR_FAULTB10_RESPONSE, PAGE = 7 MFR_FAULTB11_RESPONSE, PAGE = 7 CHANNEL 7 EVENT PROCESSOR PAGE = 7 CHANNEL 6 EVENT PROCESSOR PAGE = 6 CHANNEL 5 EVENT PROCESSOR PAGE = 5 CHANNEL 4 EVENT PROCESSOR PAGE = 4
MFR_FAULTB10_PROPAGATE, PAGE = 4 MFR_FAULTB11_PROPAGATE, PAGE = 4 MFR_FAULTB10_PROPAGATE, PAGE = 5 MFR_FAULTB11_PROPAGATE, PAGE = 5 MFR_FAULTB10_PROPAGATE, PAGE = 6 MFR_FAULTB11_PROPAGATE, PAGE = 6 MFR_FAULTB10_PROPAGATE, PAGE = 7 MFR_FAULTB11_PROPAGATE, PAGE = 7
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FAULTB10
FAULTB11
Figure 13. Channel Fault Management Block Diagram
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Interconnect Between Multiple LTC2978s Figure 14 shows how to interconnect the pins in a typical multi-LTC2978 array. * All VIN_SNS lines should be tied together in a star type connection at the point where VIN is to be sensed. This will minimize timing errors for the case where the ON_OFF_CONFIG is configured to start the LTC2978 based on VIN and ignore the CONTROLn line and the OPERATION command. In multi-part applications that are sensitive to timing errors, it is recommended that the Vin_share_enable bit of the MFR_CONFIG_ALL register be set high in order to allow SHARE_CLK to synchronize on/off sequencing in response to the VIN_ON and VIN_OFF thresholds. * Connecting all VIN_EN lines together will allow an overvoltage (OV) fault on any DC/DC converter's output in the array to shut off a common input switch. * ALERTB is typically one line in an array of PMBus converters. The LTC2978 allows a rich combination of faults and warnings to be propagated to the ALERTB pin. * WDI/RESET can be used to put the LTC2978 in the power-on reset state. Pull WDI/RESET low for at least tRESETB to enter this state. * The FAULTBzn lines can be connected together to create fault dependencies. Figure 14 shows a configuration where a fault on any FAULTBzn will pull all others low. This is useful for arrays where it is desired to abort a startup sequence in the event any channel does not come up (see Figure 15). * PWRGD reflects the status of the outputs that are mapped to it by the MFR_PWRGD_EN command. Figure 14 shows all the PWRGD pins connected together, but any combination may be used.
TO VIN OF DC/DCs TO HOST CONTROLLER LTC2978 1 VIN_SNS VIN_EN SDA SCL ALERTB CONTROL0 CONTROL1 WDI/RESET FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK PWRGD GND
TO INPUT SWITCH LTC2978 #n VIN_SNS VIN_EN SDA SCL ALERTB CONTROL0 CONTROL1 WDI/RESET FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK PWRGD GND
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TO OTHER LTC2978s-10k EQUIV PULL-UP RECOMMENDED ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
Figure 14. Typical Connections Between Multiple LTC2978s
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Trimming and Margining DC/DC Converters with External Feedback Resistors Figure 16 shows a typical application circuit for trimming/margining a power supply with an external feedback network. The VSENSEP0 and VSENSEM0 differential inputs sense the load voltage directly, and a correction voltage is developed between the VDACP0 and VDACM0 pins by the closed-loop servo algorithm. VDACM0 is Kelvin connected to the point-of-load GND in order to minimize the effects of load induced grounding errors. The VDACP0 output is connected to the DC/DC converter's feedback node through resistor R30.
VCONTROLn VOUT0 TON_DELAY0 TON_DELAY1 TON_DELAY2 * * * TON_DELAYn * * *
VOUT1 VOUT2
VOUTn BUSSED VFAULTBzn PINS
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TON_MAX_FAULT1
Figure 15. Aborted On Sequence Due to Channel 1 Short
VIN 4.5V < VIBUS < 15V 0.1F VPWR VDD33 VDD33 VDD25 0.1F LTC2978* VDACM0 VSENSEM0 VOUT_EN0 GND VIN_SNS VDACP0 VSENSEP0 LOAD R10 R30 R20
VIN VOUT DC/DC CONVERTER VFB SGND RUN/SS GND
2978 F16
*SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 16. Application Circuit for DC/DC Converters with External Feedback Resistors
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4-Step Resistor Selection Procedure for DC/DC Converters with External Feedback Resistors The following 4-step procedure should be used to calculate the resistor values required for the application circuit shown in Figure 16. 1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage VDC0(NOM), and solve for R10. VDC0(NOM) is the output voltage of the DC/DC converter when the LTC2978's VDACP0 pin is in a high impedance state. R10 is a function of R20, VDC0(NOM), the voltage at the feedback node (VFB) when the loop is in regulation, and the feedback node's input current (IFB). R20 * VFB0 R10 = VDC(NOM) - IFB0 * R20 - VFB (1) 3. Solve for the minimum value of VDACP0 that's needed to yield the minimum required DC/DC converter output voltage VDC0(MIN). The voltage-buffered current DAC has two full-scale settings, 1.33V 3.7% and 2.7V 3.7%. In order to select the appropriate full-scale setting, calculate the maximum required VDAC0P output voltage: VDACP0 > VDC(NOM) - VDC(MIN) *
(
)
R30 + VFB R20
(3)
4. Recalculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution. VDC(NOM) = VFB * 1 + R20 + IFB * R20 R10 (4)
2. Solve for the value of R30 that yields the maximum required DC/DC converter output voltage VDC0(MAX). When VDACP0 is at 0V, the output of the DC/DC converter is at its maximum voltage. R30 R20 * VFB VDC(MAX ) - VDC(NOM) (2)
R20 * VDACP0(F / S) - VFB (5) R30 R20 VDC0(MAX ) = VDC(NOM) + *V (6) R30 FB R20 * VDACP0(F / S) VRES = R30 V/DACLSB (7) 1024 VDC0(MIN) = VDC0(NOM) -
(
)
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Trimming and Margining DC/DC Converters with a TRIM Pin Figure 17 illustrates a typical application circuit for trimming/margining the output voltage of a DC/DC converter with a TRIM Pin. The LTC2978's VDACPn pin connects to the TRIM pin through resistor R30, and the VDACM0 pin is connected to the converter's point-of-load ground. DC/DC converters with a TRIM pin are typically margined high or low by connecting an external resistor between the TRIM pin and either the VSENSEP or VSENSEM pin. The relationships between these resistors and the % change in the output voltage of the DC/DC converter are typically expressed as: RTRIM _ DOWN = RTRIM _ UP = V * 100 + UP % 50 RTRIM * DC - - 1 UP % 2 * VREF * UP % RTRIM * 50 - RTRIM DOWN % (8) UP% and DOWN% denote the percentage change in the converter's output voltage when margining up or down, respectively. 2-Step Resistor and DAC Full-Scale Voltage Selection Procedure for DC/DC Converters with a TRIM Pin The following 2-step procedure should be used to calculate the resistor value for R30 and the required full-scale DAC voltage (refer to Figure 17). 1. Solve for R30: 50 - DOWN % R30 RTRIM * DOWN % (10)
2. Calculate the maximum required output voltage for VDACP0: % VDACP0 1+ UP * VREF DOWN % (11)
(
)
(9)
where RTRIM is the resistance looking into the TRIM pin, VREF is the TRIM pin's open-circuit output voltage and VDC is the DC/DC converter's nominal output voltage.
VIN 4.5V < VIBUS < 15V 0.1F VPWR VDD33 VDD33 VDD25 0.1F LTC2978* VDACM0 VSENSEM0 VOUT_EN0 GND VIN_SNS VDACP0 VSENSEP0 LOAD R30 VIN VOUT+ TRIM VSENSE+ DC/DC CONVERTER VSENSE- ON/OFFB GND
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*SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 17. Application Circuit for DC/DC Converters with Trim Pin
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LTC2978 applicaTions inForMaTion
Measuring Current Odd numbered ADC channels may be used to measure supply current. Set the ADC to high resolution mode to configure for current measuring and improve sensitivity. Note that no OV or UV faults or warnings are reported in this mode, but telemetry is available from the READ_VOUT command using the 11-bit signed mantissa plus 5-bit signed exponent linear data format. Set the MFR_CONFIG bit b[9] = 1 in order to enable high res mode. Note: Any channel configured for ADC high res mode should be permanently commanded off, i.e., OPERATION register = `h00 (this is the factory default EEPROM value). The VOUT_ENn will assert low in this mode and cannot be used to control a DC/DC. The VDACPn output is also unavailable. A circuit for measuring current is shown in Figure 18. The balanced filter, RCM, CCM, rejects common mode and differential mode noise from the inductor of the switching DC/DC converter. The filter to the ADC is placed directly across the inductor or a sense resistor in series with the inductor. Note that the + input to the ADC must be limited to <6V above ground. Select RCM and CCM such that the corner frequency is 1/10 the DC/DC converter switching frequency and 1/10 of the internal 62.5kHz clock of the LTC2978's ADC. This will assure that the DC value at the (+) input to the ADC will be equal to the output voltage with small ripple. Good values are RCM = 100, CCM 1F Keep RCM 100 to minimize gain errors due . to ADC input resistance. Many switching regulator control ICs derive AC inductor current information from an RC network such as the one formed by R1, C1, R2 and C2. The proper placement of the balanced common mode filter for the ADC input is also shown in Figure 18.
RCM CCM RCM L DCR CCM
LTC2978
+ -
ADC
+
LOAD CURRENT C1 R1 R2 C2
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-
TO CONTROLLER IC
+ -
Figure 18. DCR Current Sensing Circuits
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LTC2978 applicaTions inForMaTion
Antialiasing Filter Considerations Extremely noisy environments may require an antialiasing filter on the input to the LTC2978's ADC. The R-C circuit shown in Figure 19 is adequate for most situations. Keep R40 = R50 200 to minimize ADC gain errors, and select a value for capacitors C10 and C20 that doesn't add too much additional response time to the OV/UV supervisor, e.g. 10s (R = 100, C = 0.10F).
VIN 4.5V < VIBUS < 15V 0.1F VPWR VDD33 VDD33 VDD25 0.1F LTC2978* VSENSEM0 VDACM0 VOUT_EN0 GND *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN VIN_SNS VDACP0 VSENSEP0 C10 C20 R40 R50 LOAD R10 R30 R20
VIN VOUT DC/DC CONVERTER VFB SGND RUN/SS GND
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Figure 19. Antialiasing Filter on VSENSE Lines
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LTC2978 applicaTions inForMaTion
Dongle Connections Figure 20 illustrates the application schematic for powering and programming one or more LTC2978's from the LTC PMBus controller in the absence of system power. Because of the controller's limited current sourcing capability, only the LTC2978's and the I2C pull-up resistors should be powered from the ORed 3.3V supply. In addition, any device sharing I2C bus connections with the LTC2978 should not have body diodes between the SDA/SCL pins and its VDD node because this will interfere with bus communication in the absence of system power.
IDEAL DIODE OR'd 3.3V 0.1F LTC4412 VIN SENSE GND GATE CTL STAT 0.1F
SYSTEM 3.3V
TP0101K-SSOT23
VPWR VDD33 VDD33 VDD25 LTC2978 PIN CONNECTIONS OMITTED FOR CLARITY SDA SCL SHARE_CLK
ISOLATED 3.3V LTC CONTROLLER HEADER SDA SCL
TO/FROM OTHER LTC2978s
WP
GND
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NOTE: LTC CONTROLLER I2C CONNECTONS ARE OPTO-ISOLATED ISOLATED 3.3V FROM CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW < 10A ISOLATED 3.3V CURRENT LIMIT = 100mA
Figure 20. LTC Controller Connections for Powering and Communicating with the LTC2978
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0
LTC2978 applicaTions inForMaTion
PCB ASSEMBLY AND LAYOUT SUGGESTIONS Bypass Capacitor Placement The LTC2978 requires 0.1F bypass capacitors between the VDD33 pins and GND, the VDD25 pin and GND, and the REFP pin and REFM pin. If the chip is being powered from the VPWR input, then that pin should also be bypassed to GND by a 0.1F capacitor. In order to be effective, these capacitors should be made of high quality ceramic dielectric such as X5R or X7R and be placed as close to the chip as possible. Exposed Pad Stencil Design The LTC2978's package is thermally and electrically efficient. This is enabled by the exposed die attach pad on the under side of the package which must be soldered down to the PCB or mother board substrate. It is a good practice to minimize the presence of voids within the exposed pad inter-connection. Total elimination of voids is difficult, but the design of the exposed pad stencil is key. Figure 21 shows a suggested screen print pattern. The proposed stencil design enables out-gassing of the solder paste during reflow as well as regulating the finished solder thickness. PC Board Layout Mechanical stress on a PC board and soldering-induced stress can cause the LTC2978's reference voltage and voltage drift to shift. A simple way to reduce these stressrelated shifts is to mount the IC near the short edge of the PC board, or in a corner. The board edge acts as a stress boundary, or a region where the flexure of the board is minimal.
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Figure 21. Suggested Screen Pattern for Die Attach Pad
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LTC2978 Typical applicaTion
0.1F 0.1F 0.1F 3.3V
14 VIN VOUT R30 R20 LOAD R10 RUN/SS SGND GND NC 40 37 VDACP0 VSENSEP0
36? 35 REFP REFM
65 GND
20 WP
19 VDD25
18 VDD33
17 VDD33
16 VPWR
34 ASEL1
33 ASEL0
15 VIN_SNS VDACP7 VSENSEP7 61 3 R37 R27 LOAD R17 SGND RUN/SS GND VOUT VIN
DC/DC CONVERTER VFB
DC/DC CONVERTER VFB
38 39
VSENSEM0 VDACM0
VSENSEM7 VDACM7
4 62
5 41 43
VOUT_EN0 VDACP1 VSENSEP1
VOUT_EN7 VDACP6 VSENSEP6
12 60 1 R36 R26 LOAD R16 SGND RUN/SS GND VOUT VIN
DC/DC CONVERTER VFB
44 42
VSENSEM1 VDACM1
VSENSEM6 VDACM6
2 59
6 VIN VOUT R32 R22 LOAD R12 RUN/SS SGND GND 45 47
VOUT_EN1 VDACP2 VSENSEP2
LTC2978
VOUT_EN6 VDACP5 VSENSEP5
11 57 63 R35 R25 LOAD R15 SGND RUN/SS GND VOUT VIN
DC/DC CONVERTER VFB
DC/DC CONVERTER VFB
48 46
VSENSEM2 VDACM2
VSENSEM5 VDACM5
64 58
7 51 49
VOUT_EN2 VDACP3 VSENSEP3
VOUT_EN5 VDACP4 VSENSEP4
10 56 53 R34 R24 LOAD R14 SGND RUN/SS GND VOUT VIN
DC/DC CONVERTER VFB
50 52 IN OUT
VSENSEM3 WDI/RESETB SHARE_CLK VDACM3 FAULTB00 FAULTB01 FAULTB10 FAULTB11 VIN_EN CONTROL0 CONTROL1
VSENSEM4 VDACM4
54 55
ALERTB
INTERMEDIATE BUS CONVERTER EN
SDA
8
PWRGD
SCL
VOUT_EN3
VOUT_EN4 23 10k 10k
9
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13 3.3V 10k 5.49k
24
25
26
27
22
28
29
30
31
32
21
3.3V
TO/FROM OTHER LTC2978s AND MICROCONTROLLER
Figure 22. LTC2978 Application Circuit with 3.3V Chip Power
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LTC2978 package DescripTion
(Reference LTC DWG # 05-08-1705 Rev C)
UP Package 64-Lead Plastic QFN (9mm x 9mm)
0.70 0.05
7.15 0.05
7.50 REF 8.10 0.05 9.50 0.05 (4 SIDES)
7.15 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP
R = 0.10 TYP
63 64 0.40 1 2 PIN 1 CHAMFER C = 0.35 0.10
PIN 1 TOP MARK (SEE NOTE 5)
7.50 REF (4-SIDES)
7.15
0.10
7.15
0.10
0.200 REF NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.00 - 0.05
(UP64) QFN 0406 REV C
0.25 BOTTOM VIEW--EXPOSED PAD
0.05
0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2978 Typical applicaTion
VIN <15V RSENSE 0.007 Q1 Si4894BDY CBYPASS VIN_SNS VPWR VCC 24.3k 10k SENSE 100 68 0.01F GATE LTC4210-3 ON TIMER GND 0.22F 0.01F 10k 2907 4.99k BAT54 VIN_EN VDD33 VDD33 VDD25 0.1F 220 REFP REFM GND 0.1F *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN MCR12DC 0.1F LTC2978* VDACM0 VSENSEM0 VOUT_EN0 SGND RUN/SS GND
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VIN
VOUT DC/DC CONVERTER LOAD VFB
VDACP0 VSENSEP0
0.1F
Figure 23. LTC2978 Application Circuit with Crowbar Protection on Intermediate Bus
relaTeD parTs
PART NUMBER LTC2970 LTC4151 LTC4210-3 LTC4412 DESCRIPTION Dual I2C Power Supply Monitor and Margining Controller High Voltage I2C Current and Voltage Monitor Hot SwapTM Controller in 6-Lead SOT-23 Package Low Loss PowerPathTM Controller in ThinSOTTM COMMENTS 14-Bit ADC with < 0.5% TUE, Dual 8-Bit IDACs with 1x Voltage Buffers 7V to 80V, 12-Bit Resolution Adjustable Analog Current Limit with Circuit Breaker, Fast Response Limits Peak Fault Current Replaces Power Supply ORing Diodes, Minimal External Components, Automatic Switching Between DC Sources, Simplifies Load Sharing with Multiple Batteries, Low Quiescent Current: 11A Complete Switch Mode Power Supply, 4.5V to 20V Input Voltage, 0.6V to 5V Output Voltage, PLL Frequency Synchronization, 1.5% Regulation Complete Switch Mode Power Supply, 2.7V to 5.5V Input Voltage, 0.6V to 5V Output Voltage, Onboard Frequency Synchronization, 1.5% Regulation
LTM(R)4601 LTM4608
8A, Low VIN DC/DC Module(R) with PLL, Output Tracking and Margining 8A, Low VIN DC/DC Module with Tracking, Margining, Multiphase and Frequency Synchronization
Module is a registered trademark of Linear Technology Corporation. PowerPath, ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0909 REV A * PRINTED IN USA
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2009

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